Reset-free delay-locked loop
AssigneeInfineon Technologies AG
InventorsHai Jie Wu, Kiat How Tan, Chin Yeong Koh
Life of this patent
Estimating the term…
Abstract
A delay locked loop (DLL) includes a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal. A phase detector receives as input the input clock signal and the delayed clock signal and outputs a signal proportional to the phase difference between the input clock signal and the delayed clock signal to provide a control voltage for adjusting the delay to the specified amount. A pulse swallower removes a pulse from the input clock signal or from the delayed clock signal to reverse the direction of the control signal.
Claims22
A delay locked loop (DLL) comprising:
- a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal;
- a phase detector for receiving as input the input clock signal and the delayed clock signal and for outputting a control signal proportional to the phase difference between the input clock signal and the delayed clock signal to adjust the delay to the specified amount;
- and
- a pulse swallower for removing a pulse from the input clock signal or from the delayed clock signal to reverse a direction of the control signal.
A delay lock loop (DLL) comprising:
- a phase detector having a first input and a second input, the first input coupled to a clock node;
- a charge pump with an input coupled to an output of the phase detector;
- a loop filter with an input coupled to an output of the charge pump;
- a variable delay with a first input coupled to an output of the loop filter, the variable delay further including a second input coupled to the clock node;
- and
- a pulse swallower with an input coupled to an output of the variable delay, the pulse swallower further including an output coupled to the second input of the phase detector.
A method of generating a clock signal, the method comprising:
- providing an input clock signal;
- delaying the input clock signal by a specified amount to produce a delayed clock signal;
- detecting a phase difference between the input clock signal and the delayed clock signal;
- generating a control signal proportional to the phase difference between the input clock signal and the delayed clock signal;
- adjusting an amount of delay in the delaying step based upon the control signal;
- and
- removing a pulse from the input clock signal or from the delayed clock signal to reverse a direction of the control signal.
Dependencies are inferred from the claim text.