Delay locked loop for use in semiconductor memory device and method thereof

A delay locked loop (DLL) for use in a semiconductor memory device, comprising:

• a delay line unit for delaying an external clock signal or an external clock bar signal according to a delay amount control signal to thereby generate a delay locked clock signal;
• a divider for dividing the delay locked clock signal by a predetermined number determined based on a column address strobe (CAS) latency to thereby generate a divided signal;
• a delay line control unit for generating the delay amount control signal based on a result of comparing a phase of the external clock signal and a delayed signal of the divided signal;
• and
• a multiplexing unit for inputting one of the external clock signal and the external clock bar signal to the delay line unit based on the delay amount control signal and the result of comparing.

A semiconductor memory device for generating a delay locked clock signal, comprising:

• a buffering unit for buffering an external clock signal and an external clock bar signal to thereby generate a rising edge clock signal and a falling edge clock signal respectively;
• a delay line unit for delaying the rising edge clock signal or the falling edge clock signal according to a delay amount control signal to thereby generate the delay locked clock signal;
• a divider for dividing the delay locked clock signal by a predetermined number determined based on a column address strobe (CAS) latency to thereby generate a divided signal;
• a phase comparator for comparing the phase of the rising edge clock signal and the phase of a delayed signal of the divided signal to thereby generate a delay increment control signal and a delay decrement control signal based on a result of the comparison;
• a shift register for generating the delay amount control signal based on the delay increment control signal and the delay decrement control signal;
• and
• a multiplexing unit for inputting one of rising edge clock signal and the falling edge clock signal to the delay line unit based on the delay amount control signal and the result of the comparison.

A clock locking method of a delay locked loop (DLL) for a clock locking operation, comprising the steps of:

• a) delaying an input clock signal according to a delay amount control signal to thereby generate a delay locked clock signal;
• b) dividing the delay locked clock signal according to a column address strobe (CAS) latency to thereby generate a divided signal;
• and
• c) generating the delay amount control signal based on a result of comparing a phase of the input clock signal and a delayed signal of the divided signal.