US 2006/0132202 A1 · System and method for synthesizing a clock at digital wrapper (FEC) and base frequencies using one precision resonator

Abstract

A precision PLL based transceiver having a single precision SAW or crystal resonator is configured to lock onto multiple different input frequencies and output generated clocks at the multiple different frequencies. The input reference frequency may be higher or lower than the resonator frequency. A fraction of two whole numbers describing a ratio of the resonator frequency to a given input frequency reference is first obtained. One of the numerator or denominator in the fraction is used to set the divide value of a first frequency divider coupling a VFO based on the resonator to a feedback input on a PFD. The other of the numerator or denominator is used to set a second frequency divider coupling the input frequency reference signal to the PFD. A first frequency multiplier is given a multiplication factor matching the divide value of the second frequency divider, and used to couple the output of the first frequency divider to the output of the PLL. Alternatively, a second frequency divider may be inserted between the reference frequency input and the PFD to match the frequency, or a multiple thereof, of the VFO output, which may bypass the first frequency divider in the feedback path to the PFD.

Claims18

Dependent claims

A system for synthesizing an output frequency, comprising;

a phase locked loop, PLL, including at least one of a phase or frequency difference detector, a first integer frequency divider, and a variable frequency oscillator having a resonant frequency component;
wherein said at least one of a phase or frequency difference detector has a feedback signal input and a reference signal input, and is effective for providing a control signal dependent on said feedback signal input and reference signal input;
wherein said variable oscillator is effective for producing a variable frequency output dependent upon said control signal, said variable oscillator has a center frequency set by said resonant frequency component and has a limited frequency adjustment range about said center frequency;
wherein said first integer frequency divider divides the frequency of said variable frequency output to produce a stepped down feedback frequency coupled to said feedback signal input;
a second integer frequency divider for accepting an input frequency signal and producing a stepped down reference frequency coupled to said reference signal input;
and
an integer frequency multiplier coupled to receive said stepped down feedback frequency and produce a stepped up output frequency signal.

4 more elements

Dependencies are inferred from the claim text.

System and method for synthesizing a clock at digital wrapper (FEC) and base frequencies using one precision resonator

Life of this patent

System and method for synthesizing a clock at digital wrapper (FEC) and base frequencies using one precision resonator

Life of this patent

Abstract

Claims18