Low-power receiver equalization in a clocked sense amplifier

A circuit for adjusting a received input signal having differential first and second signal halves, the circuit comprising:

• a. a first current-steering leg having:
• i. a first input node to receive the first signal half,
• ii. a first output node;
• iii. a first tail node;
• iv. first and second current-steering devices each having a first terminal coupled to the first input node, a second terminal coupled to the first output node, and a third terminal coupled to the first tail node;
• and
• v. a first filter;
• vi. wherein the first terminal of at least one of the first and second current-steering devices is coupled to the first input node via the first filter;
• b. a second current-steering leg having:
• i. a second input node to receive the second signal half;
• ii. a second output node;
• iii. a second tail node;
• iv. third and fourth current-steering devices each having fourth terminal coupled to the second input node, a fifth terminal coupled to the second output node, and a sixth terminal coupled to the second tail node;
• and
• v. a second filter;
• vi. wherein the fourth terminal of at least one of the third and fourth current-steering devices is coupled to the second input node via the second filter.

A system for equalizing an input signal on a respective input terminal, the system comprising:

• a. a first transistor having a first current-handling terminal, a second current-handling terminal, and a first control terminal coupled to the input terminal;
• b. a second transistor having a third current-handling terminal, a fourth current-handling terminal, and a second control terminal;
• and
• c. a filter coupled between the input terminal and the second control terminal, the filter exhibiting a negative three (−3) db frequency.

A method for adjusting an input signal, the method comprising:

• a. dividing the input signal into at least two signal components, including a first signal component having first spectral content and a second signal component having second spectral content;
• b. periodically amplifying the first signal component to create a first amplified signal component;
• c. periodically amplifying the second signal component to create a second amplified signal component;
• and
• d. summing the first and second amplified signal components.

A computer-readable medium having stored thereon a data structure defining a receiver adapted to receive an input signal expressed as a sequence of data symbols, the data structure comprising:

• a. first data representing a first transistor having a first current-handling terminal, a second current-handling terminal, and a first control terminal;
• b. second data representing a second transistor having a third current-handling terminal, a fourth current-handling terminal, and a second control terminal;
• and
• c. third data representing a high-pass filter coupled between the first and second control terminals.

A differential receiver comprising:

• a. differential first and second input nodes to receive respective first and second differential signal components;
• b. a first leg including:
• i. a first transistor having a first current-handling terminal, a second current-handling terminal, and a first control terminal coupled to the first input node;
• ii. N second transistors, each having a third current-handling terminal, a fourth current-handling terminal, and a second control terminal;
• and
• iii. a first filter coupled between the first input node and at least one of the second control terminals of the N second transistors;
• and
• c. a second leg including:
• i. a third transistor having a first current-handling terminal, a second current-handling terminal, and a first control terminal coupled to the second input node;
• ii. N fourth transistors, each having a third current-handling terminal, a fourth current-handling terminal, and a second control terminal;
• and
• iii. a second filter coupled between the second input node and at least one of the second control terminals of the N fourth transistors.

A circuit comprising:

• a. first and second input nodes to receive respective first and second input-signal portions;
• b. first and second filters coupled to the respective first and second input nodes, the first filter to split the first input signal into a first signal portion and a filtered second signal portion, the second filter to split the second input signal into a third signal portion and a filtered fourth signal portion;
• c. first and second amplifier legs to amplify the respective first and third signal portions and to provide the resulting amplified first and third signal portions on respective first and second output nodes;
• d. third and fourth amplifier legs to amplify the respective filtered second and fourth signal portions and to provide the resulting amplified second and fourth signal portions on the respective first and second output nodes to combine with the respective amplified first and third signal portions.