Clock gating circuit
AssigneeVIA Technologies, Inc.
InventorJung Ham
Life of this patent
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Abstract
Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises providing a schematic layout of a D-type flip-flop, wherein the flip-flop has a reset terminal and two latches. The method further comprises modifying the layout of the flip-flop to create a clock gating circuit.
Claims17
A clock gating circuit having a modified schematic layout, the modified schematic layout being derived from the schematic layout of a D-type flip-flop having a first latch, a second latch, a VDD terminal, a data D terminal, a clock CK terminal, a reset R terminal, and an output Q terminal, the first latch comprising a first parallel-connected reset transistor and a first series-connected reset transistor, the second latch comprising a second parallel-connected reset transistor and a second series-connected reset transistor, the schematic layout of the D-type flip-flop being configured such that the reset R terminal is connected to the first parallel-connected reset transistor, first series-connected reset transistor, second parallel-connected reset transistor, and second series-connected reset transistor, wherein the modified schematic layout is derived from the schematic layout of the D-type flip-flop by removing the connection from the reset R terminal to the first parallel-connected reset transistor and first series-connected reset transistor and tying the first parallel-connected reset transistor and first series-connected reset transistor to the VDD terminal.
A method for designing a clock gating circuit, the method comprising:
- providing a schematic layout of a D-type flip-flop, the flip-flop having a reset terminal and two latches;
- and
- modifying the layout of the flip-flop to create a clock gating circuit layout.
A method for designing a clock gating circuit, the method comprising:
- providing a schematic layout of a first circuit having a reset terminal, a first latch, and a second latch, the first latch comprising a first pair of reset transistors, the second latch comprising a second pair of reset transistors;
- tying the first pair of reset transistors of the first latch to a constant logic high source;
- and
- connecting the second pair of reset transistors of the second latch to the reset terminal.
Dependencies are inferred from the claim text.