Pin multiplexing
AssigneeInfineon Technologies AG
InventorsIngo Volkening, Hong Lee Koo, Jasmeet Singh Narang, Jiaxiang Shi
Life of this patent
Estimating the term…
Abstract
There is provided a semiconductor device for multiplexing across a plurality of shared Input/Output (I/O) pins. The semiconductor device comprises a first core for operation of a first function, a second core for operation of a second function, a multiplexer and an additional hardware module. The multiplexer is arranged to set the I/O pins to the first function or to the second function at power up. The hardware module comprises an arbiter arranged to receive requests from the cores for use of the I/O pins and to grant use of the I/O pins to a selected core as required. Thus, the hardware module can switch functions dynamically and dual mode multiplexing is enabled.
Claims17
A semiconductor device for multiplexing across a plurality of Input/Output (I/O) pins, the semiconductor device comprising:
- a first core for operation of a first function;
- a second core for operation of a second function;
- a multiplexer arranged to set the I/O pins to the first function or to the second function at power up;
- and a hardware module comprising an arbiter arranged to receive requests from the cores for use of the I/O pins, and to grant use of the I/O pins to a selected core, as required.
A hardware module for a semiconductor device for multiplexing across a plurality of Input/Output (I/O) pins, the semiconductor device comprising a first core for operation of a first function, a second core for operation of a second function and a multiplexer arranged to set the I/O pins to the first function or to the second function at power up, the hardware module comprising an arbiter arranged to receive requests from the cores for use of the I/O pins, and to grant use of the I/O pins to a selected core, as required.
A method for multiplexing across a plurality of Input/Output (I/O) pins, between a first core and a second core on a semiconductor device, the first core being arranged for operation of a first function, the second core being arranged for operation of a second function, the method comprising the steps of:
- a) providing a hardware module on the semiconductor device, the hardware module comprising an arbiter;
- b) the first core and/or the second core sending a request to the arbiter for use of the I/O pins;
- c) the arbiter granting the request of a selected core;
- and
- d) the selected core receiving and/or sending data over the I/O pins.
A semiconductor device for multiplexing across a plurality of Input/Output (I/O) pins, the semiconductor device comprising a Flash core;
- a PCI (Peripheral Component Interconnect) core;
- a multiplexer arranged to set the I/O pins to Flash function at power up;
- and a hardware module comprising a PCI arbiter and a modified Flash arbiter, the PCI arbiter arranged to receive requests from the Flash core and the PCI core for use of the I/O pins and to grant use of the I/O pins to a selected core as required, the modified Flash arbiter being arranged to interface between the Flash core and the PCI arbiter.
Dependencies are inferred from the claim text.