Integrated circuit device with controllable on-die impedance

An impedance comprising:

• a. first and second nodes;
• b. a plurality of impedance legs coupled between the first and second nodes, each leg including at least one transistor having first and second current-handling terminals and a control terminal, the at least one transistor exhibiting a first impedance response to fluctuations in at least one of temperature and voltage;
• c. a feedback leg having a feedback node and exhibiting a second impedance response to the fluctuations;
• and
• d. a comparator having a first input terminal coupled to a reference, a second input terminal coupled to the feedback node, and an output terminal coupled to the control terminals of the plurality of transistors.

A method of establishing and maintaining an impedance between first and second circuit nodes, the method comprising:

• a. selectively enabling parallel current paths through a subset of a plurality of transistors coupled between the first and second nodes, each of the transistors having a control terminal and exhibiting a first impedance response to fluctuations in at least one of temperature and voltage;
• b. developing a compensation signal in response to the fluctuations;
• and
• c. controlling the impedance of the subset of the plurality of transistors in response to the compensation signal.

A resistance comprising:

• a. first and second nodes;
• b. a plurality of impedance legs extending in parallel between the first and second nodes, each impedance leg including a transistor having a first current-handling terminal coupled to the first node, a second current-handling terminal coupled to the second node, and a control terminal;
• c. means for selectively enabling a subset of the plurality of impedance legs;
• and
• d. means for developing a control voltage responsive to at least one of temperature and voltage fluctuations and for applying the control voltage to the control terminals of the transistors in the enabled subset of the plurality of impedance legs.

A computer-readable medium having stored thereon a data structure defining a differential driver, the data structure comprising:

• a. first data representing first and second nodes;
• b. second data representing a plurality of impedance legs coupled between the first and second nodes, each leg including at least one transistor having first and second current-handling terminals and a control terminal;
• c. third data representing a feedback leg having a feedback node, the feedback leg specified as including a feedback transistor similar to the at least one transistor in each leg;
• and
• d. fourth data representing a comparator having a first input terminal coupled to a reference, a second input terminal coupled to the feedback node, and an output terminal coupled to the control terminals.