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US 2006/0132169 A1Published application
Circuit re-synthesis and method for delay variation tolerance
AssigneeNational Tsing Hua University
InventorShih-Chieh Chang
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Abstract
By adding redundant logic gates into a circuit without changing function of the whole circuit, the present invention can tolerate certain delay variations. The present invention can be applied in the IC industries to improve the yield in semiconductor manufacturing.
Claims19
A circuit structure for delay variation tolerance, comprising:
- a set of voting machines;
- an original circuit, wherein some outputs of said original circuit are connected to first inputs of said voting machines;
- a first redundant circuit, wherein some outputs of said first redundant circuit are connected to second inputs of said voting machines;
- and
- a second redundant circuit, wherein some outputs of said second redundant circuit are connected to third inputs of said voting machines.
2 more elements
A circuit re-synthesis for delay variation tolerance, comprising:
- a set of logic gates;
- an original circuit, wherein some outputs of said original circuit are connected to first inputs of said logic gates;
- and
- a redundant circuit, wherein some outputs of said redundant circuit are connected to second inputs of said logic gates.
1 more element
Dependencies are inferred from the claim text.