Contactless wafer level burn-in
OwnerJian Cheninventor
Life of this patent
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Abstract
A method and apparatus for performing a wafer-level burn-in. The method comprises the steps of providing the wafer into a burn-in chamber; and outputting a power and a test initiation signal to a wafer via a wireless signal. The apparatus includes a test chamber, a transport mechanism in the test chamber, a temperature control apparatus in the test chamber, and an RF transponder in the chamber.
Claims62
A method for performing a wafer-level test sequence, comprising:
- providing the wafer into a test chamber;
- and
- outputting a power and a test initiation signal to a wafer via a wireless signal.
A method for providing a built-in test process, comprising:
- providing a built-in test circuit on the wafer;
- and
- providing an RF interface on the wafer coupled to the built-in test circuit.
A semiconductor wafer, comprising:
- at lease one built-in test control circuit coupled to a device on the wafer;
- and
- an RF interface coupled to provide power and a data signal to the BIST circuit.
A semiconductor wafer, including a plurality of dies, each die separated by a scribe line, comprising:
- at least on RF interface circuit provided on the wafer;
- at least one scribe line RF antenna coupled to the at least one RF interface circuit;
- and
- at least one burn-in voltage control circuit coupled to the RF interface.
A built-in self test circuit provided on a semiconductor wafer die, comprising:
- a device interface outputting voltage controls to induce a stress in selected components of a device;
- and
- an RF interface including a power rectifier and a signal demodulator.
An apparatus for burn-in self testing, comprising:
- a test chamber;
- a transport mechanism in the test chamber;
- a temperature control apparatus in the test chamber;
- and
- an RF transponder in the chamber.
A method for manufacturing a semiconductor device, comprising:
- fabricating a plurality of devices on a semiconductor wafer;
- performing built-in self testing of each of the devices by coupling power and control signals to the wafer via an RF signal;
- testing the devices;
- and
- separating the devices from the wafer.
A non volatile memory system, comprising:
- an array of storage elements and control circuitry;
- a BIST circuit coupled to the control circuitry;
- and
- an RF interface coupled to the BIST circuit.
Dependencies are inferred from the claim text.