Organic light emitting display and method of fabricating the same

A method of fabricating an organic light emitting display, comprising:

• forming channel regions of transistors and first electrodes of capacitors on a substrate, wherein the channel regions of transistors and first electrodes of capacitors comprise polysilicon;
• forming a first insulating layer on the channel regions of the transistors and the first electrodes of the capacitors;
• forming scan lines and second electrodes of the capacitors on the first insulating layer, wherein adjacent second electrodes of the capacitors are electrically connected with each other and wherein the second electrodes of the capacitors are arranged in a line substantially parallel to the scan lines;
• forming a second insulating layer on the scan lines and the second electrodes of the capacitors;
• forming contact holes in the second insulating layer so that the contact holes expose the second electrodes of the capacitors;
• and
• forming data lines and pixel power source lines on the second insulating layer, wherein the pixel power source lines are electrically connected with the second electrodes of the capacitors through the contact holes.

A method of fabricating an organic light emitting display, comprising:

• forming a channel region of a first transistor, a channel region of a second transistor, a channel region of a third transistor, a channel region of a fourth transistor, a channel region of a fifth transistor, a first electrode of a first capacitor, and a first electrode of a second capacitor on a substrate, wherein the channel region of the first transistor, the channel region of the second transistor, the channel region of the third transistor, the channel region of the fourth transistor, the channel region of the fifth transistor, the first electrode of the first capacitor, and the first electrode of the second capacitor comprise polysilicon;
• forming a first insulating layer on the channel region of the first transistor, the channel region of the second transistor, the channel region of the third transistor, the channel region of the fourth transistor, the channel region of the fifth transistor, the first electrode of the first capacitor, and the first electrode of the second capacitor;
• forming scan lines, emission control lines, a second electrode of the first capacitor, and a second electrode of the second capacitor on the first insulating layer, wherein adjacent second electrodes of the capacitors are electrically connected with each other and wherein the second electrodes of the capacitors are arranged in a line substantially parallel to the scan lines;
• forming a second insulating layer on the scan lines, the emission control lines, the second electrode of the first capacitor, and the second electrode of the second capacitor;
• forming contact holes in the second insulating layer so that the contact holes expose the second electrodes of the first capacitors;
• and
• forming data lines, pixel power source lines, and the first electrodes of third capacitors on the second insulating layer, wherein the pixel power source lines are electrically connected with the second electrodes of the first capacitors through the contact holes.