Pixel and light emitting display using the same

A pixel comprising:

• an OLED;
• a second transistor having a first terminal connected to a data line and having a gate terminal connected to an nth (n is a natural number) scan line;
• a first transistor having a first terminal connected to the second terminal of the second transistor;
• a third transistor having a first terminal and a gate terminal each connected to the gate terminal of the first transistor and having a second terminal connected to an (n−1)th scan line;
• a fourth transistor connected between the gate terminal and the second terminal of the first transistor and having a gate terminal connected to the nth scan line;
• a fifth transistor connected between a first power source and the first terminal of the first transistor and having a gate terminal connected to an emission control line;
• and
• a sixth transistor connected between the second terminal of the first transistor and the OLED and having a gate terminal connected to the emission control line,
• wherein the third transistor is formed to have a conductivity type different from the conductivity type of the first transistor.

A light emitting display comprising:

• a data driver configured to supply a plurality of data signals to a plurality of data lines;
• a scan driver configured to sequentially supply a plurality of scan signals to a plurality of scan lines and to supply an off voltage to the scan lines during periods when the scan signals are not supplied, wherein the off voltage has a value greater than the value of the voltage of the data signals;
• and
• an image display comprising a plurality of pixels connected to one or more of the data lines and to one or more of the scan lines,
• wherein each of the pixels comprises one or more transistors and a first of the one or more transistors is of a first conductivity type and a second of the one or more transistors is of a second conductivity type, and
• wherein a third of the one or more transistors is connected to an nth (n is a natural number) scan line and a fourth of the one or more transistors is connected to an (n−1)th scan line.