Manufacturing method of a quad flat no-lead package structure
AssigneeUnited Microelectronics Corp.
InventorsJui-Hsiang Pan, Kuang-Shin Lee, Cheng-Kuang Sun
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Abstract
The present invention provides a method for fabricating a quad flat no-lead package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.
Claims16
A method for fabricating a quad flat no-lead package structure, comprising:
- providing a substrate;
- forming a plurality of metal blocks on the substrate;
- forming an interconnect layer covering the metal blocks, wherein the interconnect layer includes a plurality of vias connecting to the metal blocks and a plurality of contact pads on a top surface of the interconnect layer, wherein the contact pads are electrically connected to the metal blocks through the vias;
- disposing at least a chip on the interconnect layer, wherein the chip includes a plurality of bonding pads corresponding to the contact pads;
- and
- removing the substrate to expose bottom surfaces of the metal blocks.
A method for manufacturing a wafer-level chip package structure, comprising:
- providing a wafer having a plurality of sections;
- forming a plurality of metal blocks on the wafer and in each of the sections of the wafer;
- forming an interconnect layer connecting the plurality of the metal blocks, wherein the interconnect layer comprises at least a via hole and a plurality of pads, wherein the via hole electrically connects one of the metal blocks and one of the pads, and wherein the pads are disposed on an uppermost surface of the interconnect layer;
- disposing at least a chip, disposed onto each of the sections of the wafer, wherein the chip includes a plurality of bonding pads that are correspondingly connected to the pads;
- and
- removing the wafer to expose bottom surfaces of the metal blocks.
The method of claim 19, wherein the step for forming the metal blocks comprises forming a metal layer over the wafer and then patterning the metal layer to form the metal blocks on the wafer.
Dependencies are inferred from the claim text.