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US 2006/0131663 A1Published application
Semiconductor device and method for manufacturing the same
AssigneeSanyo Electric Co., Ltd.
InventorNobuji Kobayashi
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AssigneeSanyo Electric Co., Ltd.
InventorNobuji Kobayashi
Estimating the term…
In a transistor, trenches are formed between each of a source region and a drain region and a channel region under the gate electrode at the position sandwiched by them. Ion implantation of impurity is carried out on the surface of the trench to form a low-concentration doped region. When the trench 50 is formed by etching, a projection 70 remains on the bottom thereof. Photoresist 86 is spin-coated on the principal surface of the semiconductor substrate where the trench 50 is formed. An opening for the photoresist 86 is installed at the part corresponding to the trench 50 and, using the photoresist 86 as a mask, ion implantation for the formation of a low-concentration doped region is performed. As a result of formation of a projection 70 in the trench, non-uniformity of film thickness of the photoresist in the trench is reduced.
A semiconductor device which includes a transistor structure equipped with a source region, a drain region and a channel region arranged on the principal surface of a semiconductor substrate, respectively, each of the source region and drain region and the channel region being separated from each other by a trench which is formed on the surface of the semiconductor substrate between them and filled with an insulating material and, along the surface of the trench, a low-concentration doped region containing lower impurity concentration than the source region and drain region is formed, characterized in that, at the bottom of the trench, at least one projection is formed.
A method for the manufacture of a semiconductor device which includes a transistor structure equipped with a source region, a drain region and a channel region arranged on the principal surface of a semiconductor substrate, respectively, each of the source region and drain region and the channel region being separated from each other by a trench which is formed between them and filled with an insulating material and, along the surface of the trench, a low-concentration doped region containing lower impurity concentration than the source region and drain region is formed, the method comprising:
A semiconductor device which is characterized in being formed by etching the principal surface of a semiconductor substrate and having trenches at a wall and bottom for ion implantation of impurity, and at least one projection remaining in the bottom of the trench in the etching.
Dependencies are inferred from the claim text.
No related US applications are recorded in the indexed filing history.
Backward citations are indexed for grants only.
Source or drain regions of field-effect devices: of igfets
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
Using masks: characterised by the angle between the ion beam and the mask
Term end not estimated
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1. Field of the Invention
The present invention relates to a semiconductor device and to a method for manufacturing the same. More particularly, it relates to a semiconductor device including a transistor structure where a trench is formed between each of a source region and a drain region and a channel region under the gate, and a lightly doped region is formed on the surface of the trench, and also relates to a method for manufacturing the same.
2. Description of the Related Art
FIG. 1 is a schematic cross-sectional view of the element illustrating the structure of the conventional medium withstand voltage transistor element utilizing an STI structure and a method for manufacturing the same.
FIG. 2 is a cross-sectional view of the element showing the conventional ion implantation step forming an LD region.
FIG. 3 is a schematic cross-sectional view showing the conventional problem in a state where photoresist which acts as a mask to the ion implantation step forming an LD region is applied.
As described hereunder, the mode for carrying out the present invention (hereinafter, referred to as embodiment) will be illustrated by referring to the drawings.
FIG. 4 is a schematic plane view of a medium withstand voltage transistor utilizing an STI structure according to the present invention. FIG. 5 is a schematic vertical cross-sectional view of FIG. 4 along the line A-A′ in the transistor. This transistor is a MOS transistor of N channels and is constituted including a source region 42, drain region 44 and channel region 46 which are formed in a P well 40 formed on the principal surface of the semiconductor substrate, and a gate electrode 48 arranged on the channel region 46. For example, the source region 42, the channel region 46 and the drain region 44 are arranged in one line. Here, its arranging direction is called a channel direction while the direction crossing it is called a channel width direction. The channel region 46 is arranged between the source region 42 and the drain region 44.
Trenches 50, 52 are formed around the source region 42, the drain region 44 and the channel region 46. Trenches 50 are formed between the source region 42 and the channel region 46 and also between the drain region 44 and the channel region 46. At the bottom of the trench 50, plural projections 70 are arranged in a matrix shape along the channel direction and the channel width direction. The trenches 52 are formed surrounding all of those regions and electrically separate the transistor from other elements arranged therearound. Silicon oxide film 54 is filled as an insulator in those trenches 50, 52.