US 2006/0131659 A1 · CMOS transistor structure including film having reduced stress by exposure to atomic oxygen

Abstract

A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

Claims10

Dependent claims

An integrated circuit including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), said NFET and said PFET each having a channel region and a source and drain region, comprising:

a PFET gate stack and an NFET gate stack formed over a substrate including a single-crystal semiconductor region, said PFET gate stack and said NFET gate stack each having a gate conductor overlying a gate dielectric formed on a main surface of said single-crystal region and spacers including a first material formed on sidewalls of said gate conductor;
a film having a stress formed over said source and drain regions of said NFET and said PFET, said stress having a reduced magnitude over said source and drain regions of either said NFET or said PFET as a result of oxidizing portions of said film over said source and drain regions of said NFET or said PFET, respectively, by exposure to atomic oxygen.

Dependencies are inferred from the claim text.

Facts

Application

11/318,844Filed 27 Dec 2005

Priority

4 Nov 2003

Published

22 Jun 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 30/792
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: comprising applied insulating layers, e.g. stress liners
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

CMOS transistor structure including film having reduced stress by exposure to atomic oxygen

Life of this patent

CMOS transistor structure including film having reduced stress by exposure to atomic oxygen

Life of this patent

Abstract

Claims10