Semiconductor integrated circuit device and method for the same
AssigneeKabushiki Kaisha Toshiba
InventorMasafumi Hamaguchi
Life of this patent
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Abstract
In a surface region of a semiconductor substrate, an element isolation region for isolating the substrate into a plurality of element regions is formed. In each of the plurality of element regions, a pair of trenches, which are formed apart from each other and each have a bottom surface and side surfaces, are formed. Further, an insulation film is formed on each of the bottom surfaces in the pair of trenches, and on the insulation film, a source region and a drain region are formed so as to embed the inside of the pair of trenches. In addition, a channel region which is interconnected to the semiconductor substrate is formed between the source region and a drain region, and a gate electrode is formed on each channel region.
Claims19
A MOS type semiconductor integrated circuit device comprising:
- an element isolation region which is formed in the surface region of a semiconductor substrate, and isolates the substrate into a plurality of element regions;
- a pair of trenches which is formed apart in each of said plurality of element regions, and each has a bottom surface and side surfaces;
- an insulation film having at least a first portion positioned on said each bottom surface in the pair of trenches;
- a source region and a drain region formed on the insulation film, and formed on the inside of the pair of trenches;
- a channel region which is formed between the source region and the drain region, and is interconnected to the semiconductor substrate;
- and
- a gate electrode formed on said each channel region.
A method of manufacturing a MOS type semiconductor integrated circuit device, comprising:
- forming an element isolation region in a surface region of a silicon semiconductor substrate, and isolating the substrate into a plurality of element regions;
- forming a gate electrode on each of said plurality of element regions;
- etching and removing the substrate by using said each gate electrode as a mask, and forming a pair of trenches in the substrate of said plurality of element regions;
- forming a silicon nitride film composed of a first portion which is positioned on the bottom surface of each of the pair of trenches, and a second portion which is positioned on the side surfaces of the trench and whose upper surface is lower than the upper surface of the substrate before etching for each trench;
- performing an epitaxial growth of silicon with the silicon substrate under the gate electrode as a seed, and forming a single crystal silicon layer on the silicon nitride film;
- flattening the upper surface of said each single crystal silicon layer;
- and
- introducing impurities into said each single crystal silicon layer and forming a source region and a drain region.
Dependencies are inferred from the claim text.