CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same

A method of fabricating a Complementary Metal Oxide Semiconductor (CMOS) device, comprising:

• forming an isolation layer in a predetermined region of a semiconductor substrate to define first and second active regions;
• forming first and second gate patterns crossing over the first and second active regions respectively;
• forming first and second dummy gate spacers on sidewalls of the first and second gate patterns respectively;
• etching the second dummy gate spacer;
• forming first elevated source/drain regions and second elevated source/drain regions on the first and second active regions respectively after etching the second dummy gate spacer;
• removing the first dummy gate spacer to form an opening;
• and
• forming a first outer gate spacer covering a sidewall of the first gate pattern which fills the opening and a second outer gate spacer disposed on edges of the second elevated source/drain regions adjacent to the second gate pattern.

A method of fabricating a Metal Oxide Semiconductor (MOS) transistor, comprising:

• forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region;
• forming a gate pattern crossing over the active region;
• forming an inner gate spacer on a sidewall of the gate pattern;
• forming a dummy gate spacer on an outer sidewall of the inner gate spacer;
• forming elevated source/drain regions on the active region adjacent to the dummy gate spacer;
• removing the dummy gate spacer to form an opening;
• implanting first impurity ions into the active region using the gate pattern, the inner gate spacer and the elevated source/drain regions as ion implantation masks to form low-concentration source/drain regions under the opening;
• forming an outer gate spacer that covers an outer sidewall of the inner gate spacer and fills the opening;
• and
• implanting second impurity ions into the active region using the gate pattern, the inner gate spacer and the outer gate spacer as ion implantation masks, thereby forming high-concentration source/drain regions and doping the elevated source/drain regions with the second impurity ions.