Transistor device and method of manufacture thereof
AssigneeInfineon Technologies AG
InventorHong-Jyh Li
Life of this patent
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Abstract
A method of forming transistors and structures thereof. A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n type dopant. The NMOS device may be doped with either an n type or a p type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided.
Claims23
A transistor, comprising:
- a workpiece, the workpiece having a region implanted with a first dopant;
- a gate dielectric disposed over the workpiece;
- a gate disposed over the gate dielectric, the gate comprising a semiconductive material and being implanted with the first dopant;
- and
- a source region and a drain region formed in the region of the workpiece, wherein the source region and the drain region are proximate the gate dielectric.
A complimentary metal oxide semiconductor (CMOS) device, comprising:
- a workpiece;
- a positive channel metal oxide semiconductor (PMOS) transistor formed in a first region of the workpiece, the PMOS transistor comprising a first gate dielectric disposed over the workpiece and a first gate disposed over the first gate dielectric, the first gate comprising a first semiconductive material comprising an n type dopant;
- and
- a negative channel metal oxide semiconductor (NMOS) transistor formed in a second region of the workpiece, the NMOS transistor comprising a second gate dielectric disposed over the workpiece and a second gate disposed over the first gate dielectric, the second gate comprising a second semiconductive material.
The CMOS device according to claim 12, wherein the first gate and the second gate comprise polysilicon, TiN, HfN, TaN, W, Al, Ru, RuTa, TaSiN, NiSix, CoSix, TiSix, Ir, Y, Pt, Ti, PtTi, Pd, Re, Rh, borides, phosphides, or antimonides of Ti, Hf, Zr, TiAlN, Mo, MoN, ZrSiN, ZrN, HfN, HfSiN, WN, Ni, Pr, VN, TiW, a partially silicided gate material, a fully silicided gate material (FUSI), or combinations thereof.
A method of manufacturing a transistor, the method comprising:
- providing a workpiece;
- implanting a first dopant into the workpiece;
- forming a gate dielectric over the workpiece;
- forming a gate over the gate dielectric, the gate comprising a semiconductive material;
- and
- implanting the first dopant into the gate.
A method of manufacturing a complimentary metal oxide semiconductor (CMOS) device, the method comprising:
- providing a workpiece;
- forming a positive channel metal oxide semiconductor (PMOS) transistor in a first region of the workpiece, the PMOS transistor comprising a first gate dielectric disposed over the workpiece and a first gate disposed over the first gate dielectric, the first gate comprising a first semiconductive material;
- implanting an n type dopant into the first semiconductive material of the first gate;
- and
- forming a negative channel metal oxide semiconductor (NMOS) transistor in a second region of the workpiece, the NMOS transistor comprising a second gate dielectric disposed over the workpiece and a second gate disposed over the second gate dielectric, the second gate comprising a second semiconductive material.
Dependencies are inferred from the claim text.