US 2006/0131650 A1 · Bipolar reading technique for a memory cell having an electrically floating body transistor

Abstract

A technique of sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, the present inventions are directed to a memory cell, having an electrically floating body transistor, and/or a technique of reading the data state in such a memory cell. In this regard, the present inventions employ the intrinsic bipolar transistor current to read and/or determine the data state of the electrically floating body memory cell (for example, whether the electrically floating body memory cell is programmed in a State “0” and State “1”). During the read operation, the data state is determined primarily by or sensed substantially using the bipolar current responsive to the read control signals and significantly less by the interface channel current component, which is negligible relatively to the bipolar component. The bipolar transistor current may be very sensitive to the floating body potential due to the high gain of the intrinsic bipolar transistor. As such, the programming window obtainable with the bipolar reading technique may be considerably higher (for example, up two orders of magnitude higher) than the programming window employing a conventional reading technique (which is based primarily on the interface channel current component.

Claims18

Dependent claims

An integrated circuit device comprising:

a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes:
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating;
and
a gate disposed over the body region;
and
wherein each memory cell includes (i) a first data state which is representative of a first charge in the body region of the transistor, and (ii) a second data state which is representative of a second charge in the body region of the transistor;
data sensing circuitry, coupled to the memory cell, to sense the data state of the memory cell;
and
wherein, in response to read control signals applied to the electrically floating body transistor, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the data sensing circuitry determines the data state of the memory cell substantially based on the bipolar transistor current.

8 more elements

An integrated circuit device comprising:

a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor consists essentially of:
a source region having impurities to provide a first conductivity type;
a drain region having impurities to provide the first conductivity type;
a body region disposed between the source region and the drain region wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type;
a gate disposed over the body region;
wherein each memory cell includes (i) a first data state which is representative of a first charge in the body region of the transistor, and (ii) a second data state which is representative of a second charge in the body region of the transistor;
data sensing circuitry, coupled to the memory cell, to sense the data state of the memory cell;
memory cell control circuitry, coupled to the memory cell, to generate and apply read control signals to the electrically floating body transistor;
and
wherein, in response to read control signals, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the data sensing circuitry determines the data state of the memory cell substantially based on the bipolar transistor current.

7 more elements

An integrated circuit device comprising:

a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the electrically floating body transistor includes:
a source region having impurities to provide a first conductivity type;
a drain region having impurities to provide the first conductivity type,
a body region disposed between the source region, the drain region and the insulating region or layer of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type;
a gate spaced apart from the body region;
wherein each memory cell includes (i) a first data state which is representative of a first charge in the body region of the transistor, and (ii) a second data state which is representative of a second charge in the body region of the transistor;
data sensing circuitry, coupled to the memory cell, to sense the data state of the memory cell;
memory cell control circuitry, coupled to the memory cell, to generate and apply read control signals to the electrically floating body transistor;
and
wherein, in response to read control signals, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the data sensing circuitry determines the data state of the memory cell substantially based on the bipolar transistor current.

7 more elements

Dependencies are inferred from the claim text.

Bipolar reading technique for a memory cell having an electrically floating body transistor

Life of this patent

Bipolar reading technique for a memory cell having an electrically floating body transistor

Life of this patent

Abstract

Claims18