Power semiconductor device

A power semiconductor device comprising:

• a first semiconductor layer of a first conductivity type having first and second surfaces respectively on upper and lower sides in a depth direction;
• a plurality of second semiconductor layers of the first conductivity type disposed on the first surface of the first semiconductor layer, at intervals in a lateral direction perpendicular to the depth direction;
• a plurality of third semiconductor layers of a second conductivity type respectively disposed between the second semiconductor layers;
• a plurality of fourth semiconductor layers of the second conductivity type respectively disposed in contact with upper portions of the third semiconductor layers between the second semiconductor layers;
• a plurality of fifth semiconductor layers of the first conductivity type respectively formed in surfaces of the fourth semiconductor layers;
• a first main electrode electrically connected to the second surface of the first semiconductor layer;
• a second main electrode electrically connected to each set of the fourth semiconductor layers and the fifth semiconductor layers;
• and
• a gate electrode facing, through a first insulating film, a channel region, which is each of portions of the fourth semiconductor layers interposed between the fifth semiconductor layers and the second semiconductor layers,
• wherein the first semiconductor layer is lower in impurity concentration of the first conductivity type than each second semiconductor layer, and each third semiconductor layer includes a fundamental portion and an impurity-amount-larger portion, such that the impurity-amount-larger portion is formed locally in the depth direction and is higher in impurity amount than the fundamental portion, where the impurity amount is defined by a total amount of impurities of the second conductivity type over a cross section in the lateral direction.