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US 2006/0131640 A1Published application
Memory array of non-volatile electrically alterable memory cells for storing multiple data
AssigneeNanostar Inc.
InventorsAndy Yu, Ying Go
Life of this patent
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Abstract
A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.
Claims8
An electrically alterable, non-volatile memory array, comprising:
- a plurality of memory strings, each memory string having
- a first connector connected to a drain of a first select transistor in the memory string,
- a second connector connected to a gate of the first select transistor,
- a third connector connected to a gate of a memory cell transistor in the memory string, and
- a fourth connector connected to a gate of a second select transistor in the memory string, wherein the plurality of memory strings are arranged in such way that the drain of the first select transistor in a first memory string is connected to a source of the second select transistor in an adjacent second memory string;
- a plurality of bit lines, wherein each bit line being connected to the first connector of every memory string;
- a plurality of first select lines, wherein each first select line being connected to the second connector of every memory string;
- a plurality of control lines, where each control line being connected to the third connector of every memory string;
- and
- a plurality of second select lines, wherein each second select line being connected to the fourth connector of every memory string.
7 more elements
Dependencies are inferred from the claim text.