Non-volatile memory device having improved erase efficiency and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSang-hun Jeon, Chung-woo Kim
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Abstract
A non-volatile memory device having an improved erase efficiency and a method of manufacturing the same are provided. The method includes: forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate on a semiconductor substrate; and performing a post treatment of the gate using an oxygen or CF4 plasma or ion implantation to increase a work function of an element forming the gate. Since the work function of the metal layer forming the gate can be further increased, an electron back tunneling can be suppressed during an erase operation.
Claims33
A method of manufacturing a non-volatile memory device, the method comprising:
- forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate comprising an element on a semiconductor substrate;
- and
- performing a post treatment on the gate using an element different from the element of the gate to increase a work function of the gate.
A method of manufacturing a non-volatile memory device, the method comprising:
- forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate a semiconductor substrate;
- and
- treating a surface of the gate using an oxygen plasma to increase a work function of the gate.
A method of manufacturing a non-volatile memory device, the method comprising:
- forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate on a semiconductor substrate;
- and
- treating a surface of the gate using a plasma of a gas comprising at least one of the halogen group elements to increase a work function of a element forming the gate.
A method of manufacturing a non-volatile memory device, the method comprising:
- forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a metal gate on a semiconductor substrate;
- treating a surface of the gate using a plasma of a gas comprising an oxygen gas or one of the halogen group elements to increase a work function of the metal gate;
- and
- forming a passivation layer on a surface of the metal gate whose surface is treated.
A method of manufacturing a non-volatile memory device, the method comprising:
- forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a metal gate on a semiconductor substrate;
- implanting ions of oxygen or one of the halogen group elements into the metal gate to increase a work function of the gate;
- and
- forming a passivation layer on a surface of the metal gate into which the ions are implanted.
A non-volatile memory device comprising:
- a tunnel dielectric layer disposed on a semiconductor substrate;
- a charge trapping layer disposed on the tunnel dielectric layer;
- a charge blocking layer disposed on the charge trapping layer;
- and
- a gate disposed on the charge blocking layer and comprising a metal layer having a work function ranging from 4.7 eV to 6.0 eV.
A non-volatile memory device comprising:
- a tunnel dielectric layer disposed on a semiconductor substrate;
- a charge trapping layer disposed on the tunnel dielectric layer;
- a charge blocking layer disposed on the charge trapping layer;
- and
- a gate disposed on the charge blocking layer and post treated by using an element different from an element of the gate to increase a work function of the gate.
Dependencies are inferred from the claim text.