Integrated two device non-volatile memory

An integrated, non-volatile memory cell comprising:

• a fixed threshold element comprising:
• a gate insulator layer formed over a substrate;
• an access gate formed over the gate insulator layer;
• a bistable element comprising:
• a tunnel insulator layer formed over the substrate;
• a charge trapping layer formed over the tunnel insulator layer;
• a charge blocking layer formed over the charge trapping layer;
• and
• a control gate formed over the charge blocking layer;
• and
• a source region and a drain region formed in the substrate.

An integrated, non-volatile memory cell comprising:

• a fixed threshold element comprising:
• a gate insulator layer formed over a substrate;
• an access gate formed over the gate insulator layer;
• a first bistable element comprising an ONO-type gate insulator stack and a first control gate;
• a second bistable element comprising the ONO-type gate insulator stack and a second control gate;
• and
• a source region and a drain region formed in the substrate.

Integrated, non-volatile memory cells comprising:

• a substrate comprising a trench that is formed between two mesas, the trench comprising opposing sidewalls;
• a first ONO-type gate insulator stack formed on a first sidewall;
• a second ONO-type gate insulator stack formed on a second, opposing sidewall;
• a source region formed in the substrate at the bottom of the trench;
• a first fixed threshold element, comprising a first access gate, formed on a first mesa;
• a second fixed threshold element, comprising a second access gate, formed on a second mesa;
• a first drain region formed in the first mesa;
• a second drain region formed in the second mesa;
• and
• a control gate formed in the trench between the opposing sidewalls and over the first and second gate insulator stacks, the control gate overlapping the first and second access gates.

Integrated, non-volatile memory cells comprising:

• a substrate comprising a trench formed between mesas, the trench comprising opposing sidewalls;
• a source region formed at each corner of the trench;
• a drain region formed at the top of each mesa;
• a fixed threshold element formed vertically along each opposing sidewall, each fixed threshold element formed substantially over at least a portion of a nearest drain region and each element comprising an access gate;
• and
• a bistable element formed vertically along each opposing sidewall substantially adjacent to the fixed threshold element along that sidewall, the bistable elements in the trench sharing a common control gate that overlaps the access gates.

An electronic system comprising:

• a processor that generates memory control signals;
• and
• a flash memory device coupled to the processor and operating in response to the memory control signals, the memory device comprising a memory array wherein each of a plurality of memory elements of the array is comprised of:
• an oxy-nitride tunnel insulator formed over a substrate;
• a trapping layer formed over the tunnel insulator;
• a charge blocking layer formed over the trapping layer;
• and
• a control gate formed over the charge blocking layer, the control gate comprising a nitride layer.

A method for fabricating a bistable memory element, the method comprising:

• forming a drain region and a source region in a substrate;
• forming a tunnel insulator layer over the substrate;
• forming a trapping layer over the tunnel insulator layer;
• forming a charge blocking layer over the trapping layer;
• forming a nitride layer over the charge blocking layer;
• and
• forming a polysilicon control gate over the nitride layer.

A method for fabricating a non-volatile memory cell, the method comprising:

• forming a fixed threshold element over a substrate, the fixed threshold element comprising:
• forming a gate insulator over the substrate;
• and
• forming an access gate over the gate insulator;
• and
• forming a first bistable element over the substrate and substantially adjacent to the fixed threshold element, the first bistable element comprising:
• forming a tunnel insulator over the substrate;
• forming a trapping layer over the tunnel insulator;
• forming a blocking layer over the trapping layer;
• and
• forming a control gate over the blocking layer.

A method for fabricating a plurality of non-volatile memory cells, the method comprising:

• forming a trench in a substrate such that the trench forms a mesa on each side;
• forming a source region in the bottom of the trench;
• forming a first drain region on a first mesa and a second drain region on a second mesa;
• forming a first bistable element on a first sidewall of the trench and a second bistable element on a second sidewall of the trench;
• forming a first fixed threshold element on the first mesa and a second fixed threshold element on the second mesa, each fixed threshold element comprising an access gate;
• and
• forming a control gate in the trench between the first and second bistable elements such that the control gate overlaps the access gates of the first and second fixed threshold elements.

A method for fabricating a plurality of non-volatile memory cells, the method comprising:

• forming a trench in a substrate such that the trench forms a mesa on each side;
• forming a source region in each corner of the bottom of the trench such that the resulting plurality of source regions are coupled together in series;
• forming a first drain region on a first mesa and a second drain region on a second mesa;
• forming a first bistable element on a first sidewall of the trench and a second bistable element on a second sidewall of the trench;
• forming a first fixed threshold element on the first sidewall substantially adjacent to the first bistable element and a second fixed threshold element on the second sidewall substantially adjacent to the second bistable element, each fixed threshold element comprising an access gate;
• and
• forming a control gate in the trench between the first and second sidewalls such that the control gate overlaps the access gates of the first and second fixed threshold elements.