Dram device having capacitor and method thereof

A method for forming a semiconductor device comprising:

• forming a first interlayer insulating layer on a semiconductor substrate having a cell array region and a peripheral circuit region;
• forming a first contact plug and a second contact plug to electrically contact the semiconductor substrate through the first interlayer insulating layer and to be positioned in the cell array region and the peripheral circuit region, respectively;
• forming an insulating layer on the first interlayer insulating layer;
• etching the insulating layer on the cell array region to form a temporary storage node hole exposing the first interlayer insulating layer and the first contact plug;
• simultaneously etching portions of the first contact plug and the first interlayer insulating layer exposed by the temporary storage node hole in the cell array region and to form a storage node hole;
• conformally forming a lower electrode layer on a surface of the semiconductor substrate having the storage node hole;
• performing a planarization process with respect to the lower electrode to remove the lower electrode layer on the insulating layer and simultaneously to form a cup-shaped lower electrode in the storage node hole;
• and
• forming a dielectric layer and an upper electrode to conformally and sequentially cover at least a bottom and an inner sidewall of the cup-shaped lower electrode.

A DRAM device comprising:

• a semiconductor substrate having a cell array region and a peripheral circuit region;
• a device isolation layer formed in the semiconductor substrate to define an active region;
• a plurality of gate patterns on the active region;
• impurity doping regions positioned on the active region at sides of the gate patterns;
• a first interlayer insulating layer covering the semiconductor substrate;
• a first contact plug formed through the first interlayer insulating layer in the cell array region to contact the impurity doping region at a side of the gate pattern and having an upper surface that is lower than an upper surface of the first interlayer insulating layer;
• a second contact plug formed through the first interlayer insulating layer in the peripheral circuit region to contact the semiconductor substrate and having an upper surface that is at a same height as the upper surface of the first interlayer insulating layer;
• a second interlayer insulating layer positioned over the first interlayer insulating layer;
• a cup-shaped lower electrode formed through portions of the second interlayer insulating layer and the first interlayer insulating layer to contact the first contact plug and separated from the gate pattern;
• and
• a dielectric layer and an upper electrode conformally and sequentially covering a bottom and an inner sidewall of the lower electrode.

A method of forming a DRAM device comprising:

• preparing a semiconductor substrate having a cell array region and a peripheral circuit region;
• forming a device isolation layer in the semiconductor substrate to define an active region;
• forming a plurality of gate patterns on the active region;
• forming a first interlayer insulating layer on the gate patterns and the semiconductor substrate;
• forming a first contact plug to contact the active region through the first interlayer insulating layer at a side of the gate pattern in the cell array region, and forming a second contact plug to contact the active region through the first interlayer insulating layer in the peripheral circuit region;
• forming an insulating layer on the first interlayer insulating layer;
• etching the insulating layer in the cell array region to form a temporary storage node hole exposing the first contact plug and the first interlayer insulating layer around the first contact plug;
• simultaneously etching upper portions of the first contact plug and the first interlayer insulating layer exposed by the temporary storage node hole to form a storage node hole;
• conformally forming a lower electrode layer on a surface of the semiconductor substrate having the storage node hole;
• performing a planarization process with respect to the lower electrode layer to remove the lower electrode layer on the insulating layer and simultaneously to form a cup-shaped lower electrode in the storage node hole;
• and
• forming a dielectric layer and an upper electrode to conformally and sequentially cover at least a bottom and an inner sidewall of the cup-shaped lower electrode.