Self-aligned schottky-barrier clamped planar DMOS transistor structure and its manufacturing methods

A self-aligned Schottky-barrier clamped planar DMOS transistor structure, comprising:

• a single crystalline-silicon substrate of a first conductivity type, wherein the single crystalline-silicon substrate comprises a lightly-doped epitaxial silicon layer being formed on a heavily-doped silicon substrate;
• a self-aligned source region being defined to be surrounded by a planar gate region, wherein the self-aligned source region comprises a moderately-doped base diffusion ring of a second conductivity type being formed in the lightly-doped epitaxial silicon layer through an implantation window, a heavily-doped source diffusion ring of the first conductivity type being formed in a surface portion of the moderately-doped base diffusion ring through the implantation window, a self-aligned source contact window being formed on a silicon surface of the lightly-doped epitaxial silicon layer surrounded by the moderately-doped base diffusion ring, the moderately-doped base diffusion ring surrounded by the heavily-doped source diffusion ring, and the heavily-doped source diffusion ring surrounded by a sidewall dielectric spacer being formed over a sidewall of the protection dielectric layer and on a side surface portion of the protection dielectric layer;
• the planar gate region being formed on a gate dielectric layer outside of the self-aligned source region, wherein the planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being formed on the gate dielectric layer, metal silicide layers being locally formed on the patterned heavily-doped polycrystalline-silicon layer through gaps formed between patterned capping dielectric layers, and refilled dielectric layers being formed to fill the gaps;
• and
• a source metal layer being at least formed over the self-aligned source contact window.

A self-aligned Schottky-barrier clamped planar DMOS transistor structure, comprising:

• a single crystalline-silicon substrate of a first conductivity type, wherein the single crystalline-silicon substrate comprises a lightly-doped epitaxial silicon layer being formed on a heavily-doped silicon substrate;
• a self-aligned source region being defined to be surrounded by a planar gate region, wherein the self-aligned source region comprises a moderately-doped base diffusion ring of a second conductivity type being formed in the lightly-doped epitaxial silicon layer through an implantation window patterned by a masking photoresist step, a lightly-doped diffusion region of the second conductivity type being formed in a middle portion beneath the moderately-doped base diffusion ring through a self-aligned implantation window formed between a pair of sacrificial dielectric spacers formed over sidewalls of the implantation window, a heavily-doped source diffusion ring of the first conductivity type being formed in a surface portion of the moderately-doped base diffusion ring through the implantation window, and a self-aligned source contact window being formed on a silicon surface of the lightly-doped epitaxial silicon layer surrounded by the moderately-doped base diffusion ring, the moderately-doped base diffusion ring surrounded by the heavily-doped source diffusion ring, and the heavily-doped source diffusion ring surrounded by a sidewall dielectric spacer being formed over a sidewall of a protection dielectric layer and on a side surface portion of the protection dielectric layer;
• the planar gate region being formed on a gate dielectric layer outside of the self-aligned source region, wherein the planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being formed on the gate dielectric layer and a patterned capping dielectric layer being formed on the patterned heavily-doped polycrystalline-silicon gate layer;
• and
• a source metal layer being at least formed over the self-aligned source contact window.