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US 2006/0131614 A1Published application
Memory cell structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
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Abstract
A memory structure that reduces soft-errors for us in CMOS devices is provided. The memory cell layout utilizes transistors oriented such that the source-to-drain axis is parallel a shorted side of the memory cell. The dimensions of the memory cell are such that it has a longer side and a shorter side, wherein the longer side is preferably about twice as long as the shorter side. Such an arrangement uses a shorter well path to reduce the resistance between transistors and the well strap. The shorter well strap reduces the voltage during operation and soft errors.
Claims33
A memory cell comprising:
- a p-well area having a first portion and a second portion, the first portion having a first pass-gate transistor and a first pull-down transistor, the second portion having a second pass-gate transistor and a second pull-down transistor;
- and
- an n-well area positioned between the first portion and the second portion, the n-well area having a first pull-up transistor and a second pull-up transistor;
- wherein
- the memory cell has a long side and a short side, the long side being at least twice as long as the short side, the short side being less than 0.485 μm, and a longitudinal axis of the p-well being parallel to the short side
- the gate of the first pass-gate transistor is electrically coupled to a word line;
- the source of the first pass-gate transistor is electrically coupled to a bit line;
- the drain of the first pass-gate transistor is electrically coupled to the drain of the first pull-down transistor;
- the source of the first pull-down transistor is electrically coupled to a Vss line;
- the drain of the first pass-gate transistor, the drain of the first pull-up transistor, the drain of the first pull-down transistor, the gate of the second pull-down transistor, and second pull-up transistor are electrically coupled;
- the drain of the second pass-gate transistor, the drain of the second pull-up transistor, the drain of the second pull-down transistor, the gate of the first pull-down transistor, and first pull-up transistor are electrically coupled;
- the source of the first pull-up transistor is electrically coupled to a Vcc line;
- the source of the second pull-up transistor is electrically coupled to the Vcc line;
- the gate of the second pass-gate transistor is electrically coupled to the word line;
- the source of the second pass-gate transistor is electrically coupled to a bit line bar;
- the drain of the second pass-gate transistor is electrically coupled to the drain of the second pull-down transistor;
- the source of the second pull-down transistor is electrically coupled to the Vss line;
- and
- a longitudinal axis along the source-to-direction of each transistor is substantially parallel to the shorter side of the memory cell.
16 more elements
A memory cell comprising:
- a p-well area having a first portion and a second portion, the first portion having a first pass-gate transistor, a second pass-gate transistor, and a first pull-down transistor, the second portion having a third pass-gate transistor, a fourth pass-gate transistor and a second pull-down transistor;
- and
- an n-well area positioned between the first portion and the second portion, the n-well area having a first pull-up transistor and a second pull-up transistor;
- wherein
- the memory cell has a long side and a short side, the long side being at least twice as long as the short side, the short side being less than 0.745 μm, and a longitudinal axis of the p-well being parallel to the short side;
- the gates of the first pass-gate transistor and second pass-gate transistor are electrically coupled to a first word line;
- the gates of the third pass-gate transistor and fourth pass-gate transistor are electrically coupled to a second word line;
- the source of the first pass-gate transistor is electrically coupled to a first bit line;
- the source of the third pass-gate transistor is electrically coupled to a second bit line;
- the drain of the first pass-gate transistor is electrically coupled to the drain of the first pull-down transistor;
- the source of the first pull-down transistor is electrically coupled to a Vss line;
- the source of the second pull-down transistor is electrically coupled to a Vss line;
- the drain of the first pass-gate transistor, the drain of the first pull-down transistor, the drain of the first pull-up transistor, the gate of the second pull-down transistor, the gate of the second pull-up transistor, and the drain of the third pass-gate transistor are electrically coupled;
- the drain of the fourth pass-gate transistor, the drain of the second pull-down transistor, the drain of the second pull-up transistor, the gate of the first pull-down transistor, the gate of the first pull-up transistor, and the drain of the second pass-gate transistor are electrically coupled;
- the source of the first pull-up transistor is electrically coupled to a Vcc line;
- the source of the second pull-up transistor is electrically coupled to the Vcc line;
- the source of the second pass-gate transistor is electrically coupled to a first complementary bit line;
- the source of the fourth pass-gate transistor is electrically coupled to a second complementary bit line;
- and
- a longitudinal axis along the source-to-direction of each transistor is substantially parallel to the shorter side of the memory cell.
17 more elements
Dependencies are inferred from the claim text.