Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential
AssigneeKabushiki Kaisha Toshiba
InventorsKoichi Kinoshita, Yasuhito Itaka, Takeshi Sugahara
Life of this patent
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Abstract
A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a filler cell is placed. At this time, using the spacer cell or filler cell, the well potential of the standard cells in the cell column is fixed.
Claims18
A semiconductor integrated circuit device comprising:
- a circuit section which is formed by arranging cell columns, each having standard cells arranged in a first direction, in a second direction crossing the first direction, the cell columns including,
- first standard cells each of which has a first and a second terminal to which a power supply voltage and the ground potential are applied, a third and a fourth terminal to which a well potential fixing potential is applied, and a transistor circuit to which the first and second terminals supply power and the third and fourth terminals apply a back gate bias, and
- second standard cells which fill up empty regions in the cell columns and apply the well potential fixing potential to the third and fourth terminals of the first standard cells.
A method of designing a semiconductor integrated circuit device, comprising:
- reading a standard cell from a library and forming a circuit by automatic layout wiring;
- searching each cell column in the formed circuit for an empty region;
- and
- placing a spacer cell or a filler cell in the empty region in the cell column searched for and fixing the well potential of the standard cells in the cell column by using the spacer cell or filler cell.
A method of designing a semiconductor integrated circuit device, comprising:
- reading a 4-terminal standard cell from a library and forming a temporary circuit by automatic layout wiring;
- measuring the operation timing of the formed temporary circuit;
- judging the measured operation timing;
- calculating the optimum value for timing adjustment on the basis of the judged operation timing;
- reading a 2-terminal standard cell from the library on the basis of the calculated optimum value for timing adjustment and making a timing adjustment by selectively replacing 4-terminal standard cells arranged in a plurality of cell columns with 2-terminal standard cells;
- forming a circuit by reperforming automatic layout wiring;
- searching each cell column in the formed circuit for an empty region;
- and
- placing a spacer cell or a filler cell in the empty region in the cell column searched for, the well potential of the 4-terminal standard cells arranged in the cell columns being fixed by using the 2-terminal standard cells and the spacer cell or filler cell.
Dependencies are inferred from the claim text.