Multi-layer circuit board with fine pitches and fabricating method thereof

A method of fabricating a multi-layer circuit board with fine pitches comprising;

• providing a core substrate, wherein the core substrate comprises a plurality of contact pads thereon;
• providing a composite layer, wherein the composite layer comprises a first dielectric layer, a second dielectric layer, and a third dielectric layer;
• laminating the first dielectric layer of the composite layer to the core substrate;
• forming a plurality of patterned openings within the third dielectric layer;
• forming a plurality of vias within the first dielectric layer and second dielectric layer;
• forming a conductive seed layer on the surface of the third dielectric layer, the patterned openings, and the vias;
• electroplating a conductive layer on the conductive seed layer for forming circuit in each patterned opening and conductive vias in each vias;
• and
• removing the electroplated conductive metal layer and the conductive seed layer over the surface of the third dielectric layer for forming a separation for each conductive circuit at each opening.

A build-up layer circuit board with fine pitches comprising:

• a core substrate having a plurality of contact pads thereon;
• a first dielectric layer formed on the surface of the core substrate;
• a second dielectric layer formed on the surface of the first dielectric layer;
• a plurality of conductive vias corresponding to the contact pads within the first dielectric layer and the second dielectric layer;
• a third dielectric layer on the surface of the second dielectric layer;
• and
• a plurality of circuit within the third dielectric layer, wherein the circuit are electrically connected to the contact pads through the conductive vias.

A build-up layer circuit board with fine pitches comprising:

• a first dielectric layer;
• a second dielectric layer formed on the surface of the first dielectric layer;
• a plurality of conductive vias within the first dielectric layer and the second dielectric layer;
• a third dielectric layer formed on the surface of the second dielectric layer,
• wherein the third dielectric layer has a plurality of patterned openings and the patterned openings further include circuits therein;
• and
• the circuits are electrically connected to the conductive vias.