Integrated circuit with a memory of reduced consumption
AssigneeDolfin Integration
InventorsAndrea Bonzo, Jean-Francois Pollet
Life of this patent
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Abstract
An integrated circuit comprising volatile memory elements, interface circuits connected to the volatile memory elements and, possibly, logic circuits not connected to the volatile memory elements and comprising first, second, and possibly third separate power supplies, the first power supply being connected to the volatile memory elements, the second power supply being connected to the interface circuits with the memory elements, and the third power supply being connected to other logic circuits.
Claims10
An integrated circuit (10) comprising volatile memory elements (20, 50) and logic interface circuits (16, 22, 52) connected to the volatile memory elements, comprising first and second separate power supplies (Vdd_M, Vdd_I), the first power supply being connected to the volatile memory elements and the second power supply being connected to the interface circuits and wherein the volatile memory elements (20, 50) comprise MOS transistors (28) of a first type, and the interface circuits (22, 52, 54) comprise MOS transistors (42) of a second type different from the first type.
A method for controlling in standby mode an integrated circuit (10) comprising volatile memory elements (20, 50) and interface circuits (16, 22, 52) connected to the volatile memory elements, comprising the steps of:
- providing a first power supply (Vdd_M) connected to the volatile memory elements;
- providing a second power supply (Vdd_I), separate from the first power supply, connected to the interface logic circuits;
- providing, for the volatile memory elements (20, 50), MOS transistors (28) of a first type and, for interface circuits (22, 52, 54), MOS transistors (42) of a second type different from the first type;
- and
- turning-off the second power supply and setting the first power supply to a non-zero minimum level capable of ensuring the conservation of the information stored in the volatile memory elements (20, 50).
Dependencies are inferred from the claim text.