DMA latency compensation with scaling line buffer
OwnerLi Sha, Qifan Huanginventors
Life of this patent
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Abstract
A video processing system configured with DMA latency compensation is disclosed. This compensation helps minimize or otherwise mitigate shortages of data to the display, thereby improving the quality of displayed video. A relatively small line buffer is used to stage data for video processing. Should an underflow of data occur (where the buffer reading process is ahead of the buffer writing process), data is read from the previous line buffer. This not only prevents shortages of data to the display, but also provides data that is more likely to be relevant to the actual scene being displayed (as compared to random data).
Claims20
A video processing system, comprising:
- a direct memory access (DMA) engine configured to facilitate transfer of video data from a storage to processing sections of the system;
- and
- a line buffer module configured to mitigate shortages of data available for display caused by latency associated with data transfers performed by the DMA engine, by reading out video data from a corresponding position in a previous line in the line buffer module when a current line is in an underflow condition.
A line buffer module configured to mitigate shortages of data available for display in a video processing system caused by latency associated with direct memory access (DMA) data transfers, comprising:
- a line buffer having a number of lines including a current line and a previous line, each of the lines for storing a line of video data;
- a write agent adapted to receive video data from a DMA engine, and to write that video data into one or more lines of the line buffer;
- and
- a read agent adapted to read out video data from a corresponding position in the previous line in the line buffer when the current line is in an underflow condition, thereby mitigating shortages of data available for display caused by the latency associated with the DMA data transfers.
A method for mitigating shortages of data available for display in a video processing system caused by latency associated with direct memory access (DMA) data transfers, comprising:
- receiving video data from a DMA engine;
- writing the received video data into one or more lines of a line buffer, including a previous line and a current line;
- and
- reading out video data from a corresponding position in the previous line in the line buffer when the current line is in an underflow condition, thereby mitigating shortages of data available for display caused by the latency associated with the DMA data transfers.
Dependencies are inferred from the claim text.