Image data synchronizer applied for image scaling device
AssigneeVXIS Technology Corp.
InventorsYuan-Hao Huang, Chiuan-Shian Chen, Chieh Yang
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Abstract
The image data synchronizer has a memory, an address write counter, an address read counter, a clock frequency modulator, and an analog/digital mixed value control oscillator. In order to prevent a read overhead to cause a disordered image, the analog/digital mixed value control oscillator is coupled to an output terminal of the clock frequency modulator to generate an output clock signal as the read clock signal for the address read counter in accordance with a clock adjustment value, so as to form the feedback compensation architecture.
Claims11
An image data synchronizer, which is connected to an output terminal of an image horizontal scaler, wherein the image horizontal scaler generates scaled pixels and at least one clock signal to the image data synchronizer, wherein the image data synchronizer comprises:
- a memory coupled to a data output terminal and a chronological output terminal of the horizontal scaler for temporary storing data output from the horizontal scaler;
- an address write counter coupled to an address write terminal of the memory to determine an address in the memory for storing data;
- an address read counter coupled to an address read terminal of the memory to determine a read sequence in the memory;
- a clock frequency modulator coupled to the address write counter and the address read counter to receive a write address and a read address output by the address write counter and the address read counter and to compute an adjustment value for a read clock signal of the address read counter;
- and
- an analog/digital mixed value control oscillator coupled to an output terminal of the clock frequency modulator to generate the read clock signal for the address read counter in accordance with the clock adjustment value.
Dependencies are inferred from the claim text.