Data drive integrated circuit with reduced size and display apparatus having the same
AssigneeSamsung Electronics Co., Ltd.
InventorJae-Hoon Lee
Life of this patent
Estimating the term…
Abstract
There is provided a display apparatus including a data drive IC. The data drive IC includes a current-mode analog to digital converter (DAC) comprising a plurality of dynamic circuits (instead of conventional level shifters). In response to an enable signal received, each of the dynamic circuits convert a bit of an image data signal received from a signal input circuit into a high voltage level and outputs the resulting signal to a current switch that outputs current to a current node connected to a pixel. The data drive IC including the dynamic circuit has reduced chip area and reduced power consumption (compared to conventional ones comprising a plurality of level-shifters).
Claims46
A display apparatus comprising:
- a pixel;
- a current source circuit configured to supply a current having a magnitude corresponding to a current control signal to the pixel;
- and
- an current control circuit configured to generate the current control signal so as to disable the current source circuit during a first phase period, and generating the current control signal so as to supply the current having a magnitude corresponding to a received image data signal to the pixel during a second phase period.
A display apparatus comprising:
- a plurality of pixels;
- and
- a plurality of digital to analog converters (DACs),
- wherein each of the DACs includes:
- a current source circuit configured to supply a current having a magnitude corresponding to a current control signal of the corresponding pixel;
- and
- an current control circuit configured to generate the current control signal so as to zero the magnitude of the current during a first phase period, and generating the current control signal so as to supply a current having a magnitude corresponding to a received image data signal of the corresponding pixel during a second phase period.
A display apparatus comprising:
- a display panel including a plurality (n) of scan lines, a plurality of data lines arranged to intersect the scan lines, and a plurality of pixels connected to the scan lines and the data lines;
- a scan driver configured to sequentially activate each of the plurality of scan lines;
- and
- a data driver configured to supply, to each of the pixels of activated scan lines, currents having magnitudes corresponding to received image data signals, the data driver including a plurality of digital-to-analog converters (DACs) connected respectively to the data lines;
- wherein each of the DACs includes:
- a current source circuit configured to supply a current, corresponding to a current control signal, through the data line connected to the corresponding pixel;
- and
- an current control circuit configured to generate the current control signal so as to set the magnitude of the current to zero during a first phase period, and during a second phase period generating the current control signal so as to supply the current at a magnitude corresponding to a received image data signal.
A method of controlling a display apparatus including a current source circuit configured to supply, to a pixel, a current having a magnitude corresponding to k bits of a current control signal, the method comprising the steps of:
- a) generating the k bits of the current control signal so as to reset the magnitude of the current to zero;
- and then
- b) generating the k bits of the current control signal so as to supply a current having a magnitude corresponding to k bits of a received image data signal.
A Digital-to-Analog Converter (DAC), comprising:
- a plurality of resistors each corresponding to one bit of a digital current control signal;
- and
- a plurality of current switches, each connected in series with a corresponding one of the resistors, between a first voltage and current output node, and having its gate connected to a corresponding bit of the digital current control signal;
- a plurality of dynamic gate circuits each configured to receive a corresponding bit of a digital data signal, and to output a corresponding bit of the digital current control signal in response to an enable signal.
Dependencies are inferred from the claim text.