Analog-to-digital converter in which settling time of amplifier circuit is reduced

An analog-to-digital converter which converts an input analog signal into a digital value in a plurality of steps, comprising:

• an analog-digital converter circuit which samples an input analog signal and converts the sampled analog signal into a digital value of a predetermined number of bits;
• a digital-to-analog converter circuit which converts an output signal of the analog-to-digital converter circuit into an analog signal;
• a first amplifier circuit which is provided parallel to the analog-to-digital circuit and amplifies the analog signal sampled by the analog-to-digital converter circuit by a predetermined amplification factor;
• a subtracting amplifier circuit with a capacitively coupled input which receives a signal at one end of a capacitor connected to an input terminal of the subtracting amplifier circuit and which samples a signal occurring at the other end of the capacitor, the subtracting amplifier circuit subtracting an output signal from the digital-to-analog converter circuit from an output signal from the first amplifier circuit,
• wherein the output signal from the digital-to-analog converter circuit is applied to the capacitor before the output signal from the first amplifier circuit is input to the capacitor.