Efficient Amplifier Sharing in a Multi-stage Analog to Digital Converter
AssigneeTexas Instruments Incorporated
InventorsPreetam TADEPARTHY, Jomy JOY
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Abstract
An analog to digital converter (ADC) containing an operational amplifier having a first pair of input terminals and a second pair of input terminals, wherein the output varies if the input signals on either of the input terminals pairs is changed in either the sampling phase or a hold phase. Such an operational amplifier is conveniently shared by two stages of a ADC, while reducing power consumption as well as errors.
Claims18
An analog to digital converter (ADC) containing a plurality of stages, wherein each stage samples a corresponding input signal in a sample phase and performs an amplification operation in a hold phase, said ADC comprising:
- an operational amplifier having a first pair of input terminals, a second pair of input terminals, and an output terminal, wherein a change of signal strength on any of said first pair of input terminals and said second pair of input terminals in either said sample phase or said hold phase causes a change in the strength of an output signal on said output terminal.
An operational amplifier having a first pair of input terminals and a second pair of input terminals, said operational amplifier comprising:
- a first transistor and a second transistor, the gate terminal of said first transistor and said second transistor providing said first pair of input terminals;
- and
- a third transistor and a fourth transistor, the gate terminal of said third transistor and said fourth transistor providing said second pair of input terminals,
- the drain terminals of said first transistor and said third transistor being coupled to each other at a first node,
- the drain terminals of said second transistor and said fourth transistor being coupled to each other at a second node,
- and a first signal formed between said first node and said second node represents an output signal of said operational amplifier.
A device comprising:
- a processor processing a plurality of digital values;
- and
- an analog to digital converter (ADC) sampling an analog signal and generating said plurality of digital values, said analog to digital converter (ADC) containing a plurality of stages, wherein each stage samples a corresponding input signal in a sample phase and performs an amplification operation in a hold phase, said ADC comprising an operational amplifier having a first pair of input terminals, a second pair of input terminals, and an output terminal, wherein a change of signal strength on any of said first pair of input terminals and said second pair of input terminals in either said sample phase or said hold phase causes a change in the strength of an output signal on said output terminal.
Dependencies are inferred from the claim text.