Non-linear distribution of voltage steps in flash-type a/d converters
AssigneeNXP B.V.
InventorFranciscus Paulus Budzelaar
Life of this patent
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Abstract
A method, apparatus, and system for converting an input voltage VIN to a digital output. A comparison of VIN with reference voltages in one or more flash-type analog-to-digital (A/D) converters generates the digital output representing VIN. If one A/D converter is used, the A/D converter is non-linear. If more than one A/D converter are used, the A/D converters are each linear.
Claims28
A flash-type analog-to-digital (A/D) converter, said A/D converter adapted to convert an input voltage VIN to a digital output, wherein VIN is within a working voltage range of the A/D converter, said working voltage range defined by a lowest voltage VREF− and a highest voltage VREF+, said A/D converter comprising:
- N reference voltages V1, V2, . . . , VN non-linearly distributed between VREF− and VREF+ and ordered according to VREF−<V1<V2< . . . <VN<VREF+, wherein N is at least 3;
- N comparators associated with said N reference voltages on a one-to-one basis, each comparator adapted to make a comparison between VIN and the reference voltage that is associated with said comparator, each comparator comprising bit-generating means for generating a binary bit that reflects a binary result of said comparison;
- and
- encoder means for generating the digital output from an analysis of the binary bits generated by said bit-generating means.
A method for converting an input voltage VIN to a digital output such that VIN falls between a lowest voltage VREF− to a maximum voltage VREF+, said method comprising:
- providing N reference voltages V1, V2, . . . , VN non-linearly distributed between VREF− and VREF+ and ordered according to VREF−<V1<V2< . . . <VN<VREF+, wherein N is at least 3;
- comparing VIN with each of the N reference voltages;
- generating a binary bit for each said comparisons, said binary bit reflecting a binary result of said comparison;
- and
- generating the digital output from an analysis of the generated binary bits.
A system for converting an input voltage VIN to a digital output, comprising:
- K linear flash-type analog-to-digital (A/D) converter apparatuses Z1, Z2, . . . , ZK respectively characterized by reference voltage step sizes ΔV1, ΔV2, . . . , ΔVK and respectively adapted to convert VIN into multibit strings S1, S2, . . . , SK, wherein ΔV1<ΔV2< . . . <ΔVK, and wherein K32;
- and
- encoder means for combining S1, S2, . . . , and SK to generate the digital output, wherein the digital output has a sufficient number of bits to preserve the accuracy that is contained within S1, S2, . . . , and SK.
A method for converting an input voltage VIN to a digital output, comprising:
- providing K linear flash-type analog-to-digital (A/D) converter apparatuses Z1, Z2, . . . , ZK respectively characterized by reference voltage step sizes ΔV1, ΔV2, . . . , ΔVK, wherein ΔV1<,ΔV2< . . . <ΔVK, and wherein K32;
- converting VIN, by converter apparatuses Z1, Z2, . . . , ZK, into multibit strings S1, S2, . . . , SK, respectively;
- and
- combining S1, S2, . . . , and SK to generate the digital output, wherein the digital output has a sufficient number of bits to preserve the accuracy that is contained within S1, S2, . . . , and SK.
Dependencies are inferred from the claim text.