System and method of oversampling high speed clock/data recovery
AssigneeProlific Technology Inc.
InventorChristine Lin
Life of this patent
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Abstract
A system and method of high speed clock/data recovery, which is used to recover the high speed clock/data through oversampling technique, wherein the internal clock with frequency lower than the high speed data is used for data recovery. Only three clocks are used in the digital circuit without involving all the oversampling clock phases to make the design timing complicated and critical. The system and method provide a simple clock structure to implement the digital circuit of high speed clock/data recovery in a robust and easy way. Furthermore a phase selection mechanism which decides the clock phase of the high speed data is provided as well.
Claims13
An oversampling high speed clock/data recovery system, comprising:
- an analog circuit, used to oversample the incoming high speed data, and serially output 4*i oversampled data;
- a serial/parallel conversion unit, including at least an internal global clock synchronizer, an inverted internal global clock synchronizer and a converter, said internal global clock synchronizer, and said inverted internal global clock synchronizer are used to synchronize the 2*i signals respectively and output them serially, and said converted converts them into 4*i parallel data bus;
- a phase selector, used to receive said parallel data bus, and generate 4*i phase selection signals based on the phase selection mechanism;
- a delaying device, used to compensate the time delay caused by phase selector;
- and
- a data multiplexer, used to select i bits of data from said parallel data bus as the high speed recovery data by making use of the recovered clock phase determined by said phase selector.
An oversampling high speed clock/data recovery method, comprising the following steps:
- receiving a high speed data;
- oversampling said high speed data through an analog circuit, and outputting 4*i serial data;
- receiving said serial data through a digital circuit including at least an internal global clock synchronizer and an inverted internal global synchronizer, which are used to synchronize 2*i data respectively and output them serially, and the serial/parallel converted, which converts said serial data into parallel data bus;
- and
- determining the clock phase of said high speed data based on said parallel data bus and selecting the i-bit data from said parallel data as the recovered data based on the phase selection mechanism.
Dependencies are inferred from the claim text.