Differential charge pump

A method of providing charge for a capacitor comprising:

• receiving an UP input signal and a DOWN input signal;
• providing current flow in a main current path between at least one current source and the capacitor in accordance with the UP input signal and the DOWN input signal;
• and
• providing current flow in a dummy current path to and from the at least one current source in accordance with the UP input signal and the DOWN input signal.

A charge pump for providing charge for a capacitor comprising:

• an output node adapted to be coupled to the capacitor;
• a buffer comprising an input coupled to the output node;
• a first current source;
• a first switch coupled to receive an UP input signal and configured to enable current flow between the first current source and the output node in accordance with a first state of the UP input signal;
• a second switch coupled to receive the UP input signal and configured to enable current flow between the first current source and an output node of the buffer in accordance with a second state of the UP input signal;
• a second current source;
• a third switch coupled to receive a DOWN input signal and configured to enable current flow between the second current source and the output node in accordance with a first state of the DOWN input signal;
• and
• a fourth switch coupled to receive the DOWN input signal and configured to enable current flow between the second current source and the output node of the buffer in accordance with a second state of the DOWN input signal.

A charge pump for providing charge for a capacitor comprising:

• an output node adapted to be coupled to the capacitor;
• a unity gain buffer comprising an input coupled to the output node;
• a first current source;
• a second current source;
• a first pair of NMOS and CMOS transistors coupled to receive a differential UP input signal and coupled to the first current source and the output node;
• a second pair of NMOS and CMOS transistors coupled to receive a differential DOWN input signal and coupled to the second current source and the output node;
• a third pair of NMOS and CMOS transistors coupled to receive the differential UP input signal and coupled to the first current source and an output node of the unity gain buffer;
• and
• a fourth pair of NMOS and CMOS transistors coupled to receive the differential DOWN input signal and coupled to the second current source and the output node of the unity gain buffer.

A unity gain buffer comprising:

• a PMOS input stage coupled to receive an input signal;
• an NMOS input stage coupled to receive the input signal;
• a current mirror coupled to mirror output current of the PMOS and NMOS input stages;
• and
• a load coupled to outputs of the PMOS and NMOS input stages.