Track-and-hold peak detector circuit

A circuit, comprising:

• a capacitor having a threshold node;
• at least one of:
• a charging circuit having a charging circuit input node to receive an input signal and a charging circuit output node coupled to the threshold node, wherein the charging circuit is adapted to provide a charging signal at the charging circuit output node to charge the capacitor to a capacitor-positive-peak voltage in accordance with a positive peak of the input signal, the charging circuit further having a charging-circuit-slope node at which a charging-circuit-slope signal is provided indicative of a slope of the capacitor-positive-peak voltage, and
• a discharging circuit having a discharging circuit input node to receive the input signal and a discharging circuit output node coupled to the threshold node, wherein the discharging circuit is adapted to provide a discharging signal at the discharging circuit output node to discharge the capacitor to a capacitor-negative-peak voltage in accordance with a negative peak of the input signal, the discharging circuit further having a discharging-circuit-slope node at which a discharging-circuit-slope signal is provided indicative of a slope of the capacitor-negative-peak voltage;
• a comparator having a first comparator input node coupled to the threshold node, a second comparator input node coupled to the input node of the at least one of the charging circuit and the discharging circuit, and a comparator output node at which a comparator output signal is provided;
• a first logic circuit having at least one first logic circuit input node coupled to at least one of the charging-circuit-slope node and the discharging-circuit-slope node and having a first logic circuit output node at which a first logic circuit output signal is provided indicative of a slope of at least one of the capacitor-positive-peak voltage and the capacitor-negative-peak voltage;
• and
• a second logic circuit having a second logic circuit input node coupled to the comparator output node, another second logic circuit input node coupled to the first logic circuit output node, and a second logic circuit output node at which a second logic circuit output signal is provided indicative of a predetermined period of time during which the comparator output signal has no transitions and further in response to a predetermined period of time during which the at least one of the capacitor-positive-peak voltage and the capacitor-negative-peak voltage has a slope approximately equal to zero.

A circuit, comprising:

• a first capacitor having a first threshold node;
• a second capacitor having a second threshold node;
• a charging/discharging circuit having at least two charging/discharging circuit input nodes to receive an input signal and an inverted input signal, at least two charging/discharging circuit output nodes coupled respectively to the first threshold node and to the second threshold node, and an enable/disable node, wherein the charging/discharging circuit is adapted to provide charging signals at the at least two charging/discharging circuit output nodes to charge the first capacitor to a first-capacitor-positive-peak voltage in accordance with a positive peak of the input signal and to charge the second capacitor to a second-capacitor-positive-peak voltage in accordance with a positive peak of the inverted input signal, and wherein the charging/discharging circuit is adapted to provide discharging signals at the at least two charging/discharging circuit output nodes to discharge the first capacitor to a first-capacitor-negative-peak voltage in accordance with a negative peak of the input signal and to discharge the second capacitor to a second-capacitor-negative-peak voltage in accordance with a negative peak of the inverted input signal, wherein the charging/discharging circuit further has at least one charging/discharging-circuit-slope node at which a respective at least one charging/discharging-circuit-slope signal is provided indicative of a slope of at least one of the first-capacitor-positive-peak voltage, the second-capacitor-positive-peak voltage, the first-capacitor-negative-peak voltage, and the second-capacitor-negative-peak voltage;
• a comparator having first differential comparator input nodes coupled to the first and second threshold nodes, second differential comparator input nodes coupled to respective ones of the at least two charging/discharging circuit input nodes, and a comparator output node at which a comparator output signal is provided;
• a first logic circuit having at least one first logic circuit input node coupled to the at least one charging/discharging-circuit-slope node and having a first logic circuit output node at which a first logic circuit output signal is provided in response to a slope of the at least one of the first-capacitor-positive-peak voltage, the second-capacitor-positive-peak voltage, the first-capacitor-negative-peak voltage, and the second-capacitor-negative-peak voltage;
• a second logic circuit having a second logic circuit input node coupled to the comparator output node, another second logic circuit input node coupled to the first logic circuit output node, and a second logic circuit output node coupled to the enable/disable node, wherein a second logic circuit output signal is provided at the second logic circuit output node in response to a predetermined period of time during which the comparator output signal has no transitions and further in response to a predetermined period of time during which the at least one of the first-capacitor-positive-peak voltage, the second-capacitor-positive-peak voltage, the first-capacitor-negative-peak voltage, and the second-capacitor-negative-peak voltage has a slope approximately equal to zero.