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US 2006/0125530 A1Published application
Track-and-hold peak detector circuit
AssigneeAllegro MicroSystems, LLC
InventorsHernan Romero, Jay Towne, Karl Scheller
Life of this patent
Estimating the term…
Abstract
A track-and-hold peak detector circuit, which can operate at low input signal frequencies, includes a capacitor to hold a peak voltage of the input signal and logic circuitry that reduces an effect of leakage current into or out of the capacitor, and therefore, provides protection against self-switching of an output signal of the peak detector circuit.
Claims30
A circuit, comprising;
- a capacitor having a threshold node;
- a selected one of:
- a charging circuit having a charging circuit input node to receive an input signal and a charging circuit output node coupled to the threshold node, wherein the charging circuit is adapted to provide a charging signal at the charging circuit output node to charge the capacitor to a voltage in accordance with a positive peak of the input signal, and
- a discharging circuit having a discharging circuit input node to receive an input signal and a discharging circuit output node coupled to the threshold node, wherein the discharging circuit is adapted to provide a discharging signal at the discharging circuit output node to discharge the capacitor to a voltage in accordance with a negative peak of the input signal;
- a comparator having a first comparator input node coupled to the threshold node, a second comparator input node coupled to the input node of the selected one of the charging circuit and the discharging circuit, and a comparator output node at which a comparator output signal is provided;
- a logic circuit having a logic circuit input node coupled to the comparator output node and a logic circuit output node at which a logic circuit output signal is provided in response to a predetermined period of time during which the comparator output signal has no transitions;
- and
- a switch having a first switch node coupled to the threshold node, a second switch node coupled to the selected one of the charging circuit input node and the discharging circuit input node, and a switch control node coupled to the logic circuit output node.
5 more elements
A circuit, comprising;
- a capacitor having a threshold node;
- a charging/discharging circuit comprising:
- a charging circuit having a charging circuit input node to receive an input signal, a charging circuit output node coupled to the threshold node, and an enable node;
- and
- a discharging circuit having a discharging circuit input node to receive the input signal, a discharging circuit output node coupled to the threshold node, and an inverted enable input node, wherein the charging circuit is adapted to provide a charging signal at the charging circuit output node to charge the capacitor to a voltage in accordance with a positive peak of the input signal and the discharging circuit is adapted to provide a discharging signal at the discharging circuit output node to discharge the capacitor to a voltage in accordance with a negative peak of the input signal;
- a comparator having a first comparator input node coupled to the threshold node, a second comparator input node coupled to the charging and discharging circuit input nodes, and a comparator output node at which a comparator output signal is provided;
- and
- a logic circuit having a logic circuit input node coupled to the comparator output node a logic circuit output node coupled to the enable input node and to the inverted enable input node, wherein a selected one of a first logic circuit output signal and a second logic circuit output signal is provided at the logic circuit output node in response to a predetermined period of time during which the comparator output signal has no output signal transitions.
5 more elements
A circuit, comprising;
- a first capacitor having a first threshold node;
- a second capacitor having a second threshold node;
- a charging/discharging circuit having at least two charging/discharging circuit input nodes to receive an input signal and an inverted input signal, at least two charging/discharging circuit output nodes coupled respectively to the first threshold node and to the second threshold node, and an enable/disable node, wherein the charging/discharging circuit is adapted to provide charging signals at the at least two charging/discharging circuit output nodes to charge the first capacitor to a voltage in accordance with a positive peak of the input signal and to charge the second capacitor to a voltage in accordance with a positive peak of the inverted input signal, and wherein the charging/discharging circuit is adapted to provide discharging signals at the at least two charging/discharging circuit output nodes to discharge the first capacitor to a voltage in accordance with a negative peak of the input signal and to discharge the second capacitor to a voltage in accordance with a negative peak of the inverted input signal;
- a comparator having first differential comparator input nodes coupled to the first and second threshold nodes, second differential comparator input nodes coupled to respective ones of the at least two charging/discharging circuit input nodes, and a comparator output node at which a comparator output signal is provided;
- and
- a logic circuit having a logic circuit input node coupled to the comparator output node and a logic circuit output node coupled to the enable/disable node, wherein a selected one of a first logic circuit output signal and a second logic circuit output signal is provided at the logic circuit output node in response to a predetermined period of time during which the comparator output signal has no transitions.
3 more elements
Dependencies are inferred from the claim text.