Differential analog logic circuit with symmetric inputs and output
OwnerHooman Darabiinventor
Life of this patent
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Abstract
A logic circuit incorporates symmetric inputs and/or a symmetric output. The logic circuit may include symmetric input circuits such that each input signal may be processed by a circuit that provides substantially identical rise times and fall times. The input circuits may provide symmetric loading of the input signals by providing a substantially identical circuit configuration for each input signal. The logic circuit may include a symmetric output circuit such that the output signals generated by the output circuit may have substantially identical rise times and fall times. Each leg of a differential output circuit may incorporate a substantially identical circuit configuration.
Claims19
A logic circuit comprising:
- a first input circuit coupled to receive a first input signal;
- a second input circuit coupled to receive a second input signal;
- wherein the first input circuit and the second input circuit are configured to provide symmetric loading of the first input signal and the second input signal;
- and
- an output circuit configured to generate an output signal;
- wherein at least one of the first input circuit, the second input circuit and the output circuit is configured to generate rising and falling edges of signals using the same type of transistor.
A method of performing a logic operation comprising:
- receiving input signals;
- providing symmetric loading for the input signals;
- generating rising and falling edges of signals using the same type of transistors;
- providing symmetric loading for output signals;
- and
- providing the output signals.
A logic circuit comprising:
- a first differential transistor pair coupled to a first input terminal to receive a first differential input signal and coupled to an output terminal to generate a differential output signal;
- a second differential transistor pair coupled to a second input terminal to receive a second differential input signal and coupled to the output terminal to generate the differential output signal;
- a third differential transistor pair coupled to the output terminal to generate the differential output signal;
- a fourth differential transistor pair coupled to the output terminal to generate the differential output signal;
- a first bias transistor coupled to receive a first leg of the second input signal and coupled to provide a first bias signal to the first differential pair;
- a second bias transistor coupled to receive a first leg of the first input signal and coupled to provide a second bias signal to the second differential pair;
- a third bias transistor coupled to receive a second leg of the second input signal and coupled to provide a third bias signal to the third differential pair;
- and
- a fourth bias transistor coupled to receive a second leg of the first input signal and coupled to provide a fourth bias signal to the fourth differential pair.
Dependencies are inferred from the claim text.