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US 2006/0125519 A1Published application
Programmable logic array
AssigneeSamsung Electronics Co., Ltd.
InventorDong-Gyu Lee
Life of this patent
Estimating the term…
Abstract
A programmable logic array (PLA) which may include an AND-plane receiving first input signals and generating logic product signals based on the first input signals, and an OR-plane receiving the logic product signals and a second input signal and generating a logic sum signal based on the logic product signals.
Claims20
A programmable logic array comprising:
- an AND-plane receiving first input signals and generating logic product signals based on the first input signals;
- and
- an OR-plane receiving the logic product signals and a delayed second input signal and generating a logic sum signal based on the logic product signals.
An OR-plane comprising:
- a receiving circuit receiving logic product signals and an input signal;
- and
- a generating circuit generating a logic sum signal based on the logic product signals.
An enable circuit comprising:
- a first switching device connecting a power terminal and an output terminal and charging the output terminal based on a first signal;
- a second switching device connecting a ground terminal and the output terminal and discharging the output terminal to a ground voltage level based on a second signal;
- and
- a control circuit generating the first signal or second signal based on a logic sum signal.
1 more element
A discharge device comprising:
- a first transistor including a gate receiving a logic sum signal, a source connected to an output terminal, and a drain, discharging the output terminal based on the logic sum signal;
- and
- a second transistor including a gate receiving an input signal, a source connected to the drain of the first transistor, and a drain connected to a ground terminal, discharging the output terminal based on the input signal.
A method of performing a logic function comprising:
- receiving input signals including first input signals and a delayed second input signal;
- generating logic product signals based on the first input signals;
- generating a logic sum signal based on the logic product signals;
- and
- varying the logic sum signal according to a logic state of the delayed second input signal.
2 more elements
Dependencies are inferred from the claim text.