RFID tag with bist circuits
AssigneeImpinj, Inc.
InventorsDennis Hara, Robert Glidden
Life of this patent
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Abstract
Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.
Claims18
An apparatus, comprising:
- an RFID tag comprising a receive signal path that flows from one or more primary inputs, said receive signal path to process an electrical receive signal originating from said inputs as a consequence of said inputs having received a wireless signal, said RFID tag also comprising a non-volatile memory, said non-volatile memory to store said RFID tag's identification, said RFID tag including built-in-self-test (BIST) logic circuitry to test said non-volatile memory while said RFID tag is being tested on wafer.
A method, comprising:
- applying a supply voltage to an RFID tag that has not yet been diced from its wafer, said RFID tag comprising non-volatile memory and built-in-self-test (BIST) logic circuitry, said supply voltage applied to said RFID tag at a die edge of said RFID tag for purposes of testing said non volatile memory on wafer, said testing comprising:
- said BIST logic circuitry generating a write data pattern;
- and,
- writing said write data pattern into said non-volatile memory.
Dependencies are inferred from the claim text.