LSI, test pattern generating method for scan path test, LSI inspecting method, and multichip module
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorTakuya Kobayashi
Life of this patent
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Abstract
Registers 119 and 120 for power control or power-off signals in an LSI are set as a dedicated chain and a control signal can be controlled desirably from the outside so that the states of the registers 119 and 120 can be monitored easily. In a test pattern generating method for a scan path test, the relation between values of the registers for the power control or power-off and power supplies to be controlled is set as an option in order to control the registers 119 and 120 for the power control or power-off. In this manner, a pattern in which the power control function or the power-off function of the LSI is taken into consideration can be produced.
Claims8
An LSI having a power control function or a power-off function, comprising:
- power terminals;
- ground terminals;
- registers, connected as a scan chain and capable of holding power control information;
- a gate circuit, capable of controlling a clock signal to be supplied to the registers;
- a clock control terminal capable of inputting a control signal for controlling the gate circuit;
- scan-in terminals capable of inputting scan signals;
- and
- scan-out terminals capable of outputting the scan signals;
- wherein:
- the control signal is supplied from the outside and the scan signals are monitored during a structured test.
A method for generating a test pattern for a scan path test on an LSI including power terminals and ground terminals and having a power control function or a power-off function, the method comprising the step of:
- generating a test pattern for testing the power control function or power-off function in accordance with power control information of the LSI stored in power control or power-off registers.
A method for inspecting an LSI including power terminals, ground terminals, registers connected as a scan chain and capable of holding power control information, a gate circuit capable of controlling a clock signal to be supplied to the registers, a clock control terminal capable of inputting a control signal for controlling the gate circuit, scan-in terminals capable of inputting scan signals, and scan-out terminals capable of outputting the scan signals;
- the method comprising the step of:
- inspecting the LSI in a power control state or a power-off state on the basis of a test pattern for inspecting a power control function or a power-off function of the LSI.
A multichip module, comprising:
- an LSI having power terminals;
- ground terminal;
- registers connected as a scan chain and capable of holding power control information;
- a gate circuit capable of controlling a clock signal to be supplied to the registers;
- a clock control terminal capable of inputting a control signal for controlling the gate circuit;
- scan-in terminals capable of inputting scan signals;
- and scan-out terminals capable of outputting the scan signals;
- a power supply module for performing power control or power-off on the LSI;
- and
- a package on which the LSI and the power supply module are mounted;
- wherein the LSI can be inspected in a power control state or a power-off state by controlling the power supply module in the multichip module during a structured test.
Dependencies are inferred from the claim text.