Capacitor-less 1T-DRAM cell with Schottky source and drain

A memory cell comprising:

• a first semiconductor layer with a first conductivity type overlying an insulating layer wherein the first semiconductor acts as a body region;
• a gate dielectric overlying the semiconductor layer;
• a gate electrode overlying the gate dielectric;
• a pair of spacers on sides of the gate electrodes;
• a first Schottky barrier junction formed on a source region and a second Schottky barrier junction formed on a drain region on opposing sides of the body region;
• wherein the source region and the drain region overlap with the gate electrode and wherein the overlap regions have a width of greater than about 5 Å;
• and
• wherein the first Schottky barrier junction region is adjacent to a second semiconductor layer and the second Schottky barrier junction region is adjacent to a third semiconductor layer.

A method of forming a memory cell, the method comprising:

• providing a first semiconductor layer of a first conductivity type overlying an insulating layer wherein the first semiconductor layer acts as a body region;
• forming a gate dielectric over the semiconductor layer;
• forming a gate electrode over the gate dielectric;
• forming a pair of spacers on sides of the gate electrodes;
• forming a first Schottky barrier junction in a source region and a second Schottky barrier junction in a drain region on opposing sides of the body region;
• wherein the first and the second Schottky barriers are under the gate electrode;
• and
• causing a net concentration of carriers of the first-type conductivity in the body region, the net concentration being resulted from GIDL-like current.