Method of fabricating polycrystalline silicon
AssigneeLG.Philips LCD Co., Ltd.
InventorYoung-Joo Kim
Life of this patent
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Abstract
A method of fabricating polycrystalline silicon according to an embodiment includes forming a semiconductor layer of amorphous silicon on a substrate having a first region and a second region surrounding the first region; forming a plurality of flat align keys in the second region using a first mask; forming a plurality of convex align keys by etching the semiconductor layer in the first region, the plurality of convex align keys having steps against the substrate; and crystallizing the semiconductor layer in the first region by aligning a second mask with respect to the plurality of convex align keys.
Claims55
A method of fabricating polycrystalline silicon, comprising:
- forming a semiconductor layer of amorphous silicon on a substrate having a first region and a second region surrounding the first region;
- forming a plurality of flat align keys in the second region using a first mask;
- forming a plurality of convex align keys from the plurality of flat align keys;
- and
- crystallizing the semiconductor layer in the first region using a second mask and using the plurality of convex align keys.
A method of fabricating an align key usable in a crystallization process of amorphous silicon, comprising:
- forming a semiconductor layer of amorphous silicon on a substrate;
- crystallizing corner portions of the semiconductor layer to form a plurality of flat align keys;
- and
- dipping the corner portions of the semiconductor layer into an etchant having an etch selectivity of polycrystalline silicon to amorphous silicon to form a plurality of align key patterns having slope against the substrate.
A method for fabricating a switching element, comprising:
- forming a semiconductor layer of amorphous silicon on a substrate having a first region and a second region surrounding the first region;
- forming a plurality of flat align keys in the second region using a first mask;
- forming a plurality of align key patterns from the plurality of flat align keys, the plurality of align key patterns having slope against the substrate;
- crystallizing the semiconductor layer in the first region by aligning a second mask with respect to the plurality of align key patterns;
- and
- selectively removing the semiconductor layer to form an active layer including a channel region and source and drain regions at sides of the channel region.
A method of fabricating polycrystalline silicon, comprising:
- forming a semiconductor layer having a first portions and second portions with an amorphous silicon on a substrate having a first region and a second region adjacent the first region;
- forming a plurality of flat align keys in the first portions of the semiconductor in the first region of the substrate using a first mask;
- forming a plurality of align key patterns in the first portions of the semiconductor;
- and
- aligning the plurality of align key patterns and crystallizing the first portions of the semiconductor in the second region of the substrate using a second mask.
Dependencies are inferred from the claim text.