Lead frame for semiconductor device
AssigneeShinko Electric Industries Co., Ltd.
InventorsKazumitsu Seki, Takashi Yoshie, Koichi Kadosaki
Life of this patent
Estimating the term…
Loading patent…
AssigneeShinko Electric Industries Co., Ltd.
InventorsKazumitsu Seki, Takashi Yoshie, Koichi Kadosaki
Estimating the term…
Lead frames of a Pd-PPF structure for use in a semiconductor device comprising inner leads and outer leads, wherein a whole surface of the substrate constituting the lead frame or at least the outer leads has a composite plated layer, and the composite plated layer comprises an underlayer consisting of an Ni-based plating layer deposited on the whole surface of the substrate constituting the lead frame or on at least the outer leads, a Pd— or Pd alloy-plating layer deposited at a thickness of 0.005 to 0.01 μm on an upper surface of the underlayer, and an Au-plating layer deposited at a thickness of 0.02 to 0.1 μm on an upper surface of the Pd— or Pd alloy-plating layer. When a semiconductor device is mounted on a packaging substrate by using a lead-free Sn—Zn-based solder or any other lead-free solder, the wettability between the lead frame and the lead-free Sn—Zn-based solder or any other lead-free solder is improved to thereby improve the packaging property of the semiconductor device.
A lead frame for use in a semiconductor device comprising inner leads and outer leads, wherein a whole surface of the substrate constituting the lead frame or at least the outer leads has a composite plated layer applied thereon, and the composite plated layer comprises an underlayer consisting of an Ni-based plating layer deposited on the whole surface of the substrate constituting the lead frame or on at least the outer leads, a Pd— or Pd alloy-plating layer deposited at a thickness of 0.005 to 0.01 μm on an upper surface of the underlayer, and an Au-plating layer further deposited at a thickness of 0.02 to 0.1 μm on an upper surface of the Pd— or Pd alloy-plating layer.
A lead frame for use in a semiconductor device comprising inner leads and outer leads, wherein a whole surface of the substrate constituting the lead frame or at least the outer leads has a composite plated layer applied thereon, and the composite plated layer comprises an underlayer consisting of an Ni-based plating layer deposited on the whole surface of the substrate constituting the lead frame or on at least the outer leads, a Pd— or Pd alloy-plating layer deposited at a thickness of 0.005 to 0.01 μm on an upper surface of the underlayer, and an Ag— or Ag—Au alloy-plating layer of a thickness of not larger than 0.03 μm and an Au-plating layer of a thickness of not larger than 0.03 μm successively deposited on an upper surface of the Pd— or Pd alloy-plating layer.
A lead frame for use in a semiconductor device comprising inner leads and outer leads, wherein a whole surface of the substrate constituting the lead frame or at least the outer leads has a composite plated layer applied thereon, and the composite plated layer comprises an underlayer consisting of an Ni-based plating layer deposited on the whole surface of the substrate constituting the lead frame or on at least the outer leads, a Pd— or Pd alloy-plating layer deposited at a thickness of 0.005 to 0.01 μm on an upper surface of the underlayer, and Ag-plating layers and Au-plating layers each having a thickness of 0.02 to 0.2 μm, alternately deposited on an upper surface of the Pd— or Pd alloyplating layer.
6-8. (canceled)
Dependencies are inferred from the claim text.