Methods of reducing floating body effect
AssigneeMicron Technology, Inc.
InventorGordon Haller
Life of this patent
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Abstract
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a preferred embodiment, a word line is recessed into the substrate to tie the upper active region to the substrate. The resulting memory cells are preferably used in dynamic random access memory (DRAM) devices.
Claims49
A method of reducing the floating body effect in a memory cell, comprising:
- forming an isolation trench within a substrate, whereby a ridge in the substrate is defined proximate to the isolation trench;
- filling the isolation trench with an insulating material;
- forming a silicon pillar over the ridge after filling the isolation trench, wherein an upper active area is located on the silicon pillar;
- forming a source region on the ridge adjacent to the silicon pillar;
- recessing the insulating material in the isolation trench below a top point of the ridge;
- depositing a word line after recessing the insulating material, wherein the word line extends lower than the top point of the ridge;
- and
- forming a capacitor over the silicon pillar after depositing the word line.
A memory array for a DRAM comprising:
- a plurality of source regions on a plurality of substrate ridges;
- a plurality of isolation trenches positioned between the substrate ridges;
- a plurality of silicon pillars positioned in columns on the substrate ridges between source regions;
- a plurality of word lines that each surround a row of silicon pillars, wherein the word lines are substantially recessed into the isolation trenches to a depth below a top point of the substrate ridges;
- a plurality of digit lines positioned above the silicon pillars;
- and
- a cell capacitor overlying each silicon pillar.
The array of claim 22, wherein the word lines comprise n-doped polysilicon.
A memory cell comprising
- a vertical transistor including:
- a source region within a ridge of semiconductor material;
- an upper active area on a silicon pillar extending above the ridge;
- and
- a gate surrounding the silicon pillar, wherein the gate is recessed into
- a trench next to the ridge;
- a cell capacitor contact plug directly over the silicon pillar;
- and
- a cell capacitor having:
- a lower electrode over and electrically connected to the cell capacitor contact plug;
- a capacitor dielectric over the lower electrode;
- and
- an upper electrode over the capacitor dielectric.
A method of forming a memory array comprising:
- defining a plurality of parallel trenches and ridges in a p-doped bulk silicon substrate;
- filling the trenches with an isolation material;
- forming a mask over the substrate to create windows on the ridges in which to form pillars;
- creating a plurality of pillars over the ridges after forming the mask;
- recessing the isolation material in the trench after forming the pillars;
- and
- depositing a plurality of word lines over the isolation oxide and the ridges and surrounding a row of pillars after forming the pillars, wherein the word lines descend substantially into the trenches on two sides of each pillar,
Dependencies are inferred from the claim text.