Electronic component and panel for producing the same

An electronic component comprising:

• a stack of semiconductor chips having a first semiconductor chip and a stacked second semiconductor chip, the semiconductor chips having an active upper face with contact pads to integrated circuits and a rear face;
• a flat conductor structure having a chip island, flat conductors surrounding the chip island, and contact pillars arranged on the flat conductors and aligned orthogonally with respect to the flat conductors;
• wherein the second semiconductor chip is arranged with its rear face on the chip island and wherein its contact pads are electrically connected via bonding wire connections to the flat conductors;
• wherein the first semiconductor chip is surrounded by the contact pillars and is arranged underneath the chip island such that pillar contact pads of the contact pillars, upper face areas of a plastic encapsulation compound that embeds the semiconductor chips, the contact pillars and the flat conductor structure, and the active upper face of the first semiconductor chip, form an overall upper face, and
• wherein a wiring layer is arranged on the overall upper face and electrically connects the semiconductor chips to one another via wiring lines.

A method for production of a panel for a plurality of electronic components

• producing leadframe with component positions arranged in rows and columns, whereby a component position comprises a chip island and flat conductors which surround the chip island, as well as contact pillars, which are arranged on the flat conductors and are aligned orthogonally with respect to the flat conductors;
• applying a stacked semiconductor chip to the chip island of the component positions;
• producing bonding wire connections between the flat conductors and contact pads on active upper faces of the stacked semiconductor chips;
• applying first semiconductor chips with their active upper faces to a carrier with adhesive bonding on one side, with the first semiconductor chips being arranged in rows and columns which correspond to the rows and columns of the component positions;
• applying the leadframe with stacked semiconductor chips to the carrier in such a way that the contact pillars of the leadframe are adhesively bonded by their upper faces to the carrier and the first semiconductor chips are arranged on the carrier underneath the chip islands of the leadframe and are surrounded by contact pillars;
• embedding the leadframe with stacked semiconductor chips and bonding wire connections in a plastic compound to form a composite body on the carrier;
• removing the carrier exposing an overall upper face composed of active upper faces of the first semiconductor chips, pillar contact pads of the contact pillars, and an upper face of the plastic compound;
• applying a wiring layer to the overall upper face, forming wiring lines and outer contact pads;
• and
• wherein the wiring lines connect the outer contact pads to the contact pads of the first semiconductor chip, and/or to the pillar contact pads of the contact pillars.

An electronic component comprising:

• a first semiconductor chip having an active upper face, contact pads, and a rear face;
• a stacked second conductor chip having an active upper face, contact pads, and a rear face;
• a chip island;
• flat conductors surrounding the chip island;
• contact pillars arranged on the flat conductors and surrounding the first semiconductor chip;
• wherein the second semiconductor chip is arranged with its rear face on the chip island;
• means for electrically connecting the contact pads of the second semiconductor chip to the flat connectors;
• a plastic encapsulation compound configured to embedd the first and second semiconductor chips, the contact pillars, the chip island, and the flat conductors;
• wherein the first semiconductor chip is arranged under the chip island such that pillar contact pads of the contact pillars, upper face areas of the plastic encapsulation compound, and the active upper face of the first semiconductor chip form an overall upper face;
• and
• means on the overall upper face for electrically connecting the first and second semiconductor chips to each other.