Vertical field effect transistor and method for fabricating the same

An electronic device comprising

• a substrate and
• a plurality of field effect transistors provided on the substrate,
• wherein at least one of the field effect transistors is a vertical field effect transistor including:
• an active region, which includes a bundle of multiple linear structures functioning as a channel region where electric carriers are transported;
• a lower electrode, which is connected to the bottom of the active region and which functions as one of source and drain regions;
• an upper electrode, which is connected to the top of the active region and which functions as the other of the source and drain regions;
• a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region;
• and
• a gate insulating film, which is arranged between the active region and the gate electrode in order to electrically isolate the gate electrode from the bundle of linear structures,
• wherein the transistor further includes a dielectric portion between the upper and lower electrodes, and
• wherein the upper electrode is located over the lower electrode with the dielectric portion interposed between the upper and lower electrodes, and includes an overhanging portion that sticks out laterally from over the dielectric portion, and
• the active region is located right under the overhanging portion of the upper electrode.

A method for fabricating a vertical field effect transistor, the transistor including:

• an active region, which includes a bundle of multiple linear structures functioning as a channel region where electric carriers are transported;
• a lower electrode, which is connected to the bottom of the active region and which functions as one of source and drain regions;
• an upper electrode, which is connected to the top of the active region and which functions as the other of the source and drain regions;
• a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region;
• and a gate insulating film, which is arranged between the active region and the gate electrode in order to electrically isolate the gate electrode from the bundle of linear structures,
• the method comprising the steps of:
• (A) forming a structure in which a dielectric portion is interposed between the upper electrode and the lower electrode and in which the upper electrode has an overhanging portion that sticks out laterally from over the dielectric portion;
• and
• (B) growing a bundle of linear structures so that the linear structures extend from an area on the upper surface of the lower electrode, which is not covered with the dielectric portion, toward the lower surface of the overhanging portion of the upper electrode.