US 2006/0125024 A1 · Semiconductor device and a method of manufacturing the same

Abstract

To improve reliability of FETs having element isolation regions for electrically isolating field effect transistors adjacent to each other in the gate length direction in a mask ROM region, the isolation regions are each constructed by field plate isolation formed simultaneously with gate electrodes of the field effect transistors. This relatively lessens a stress generated in an active region ACT sandwiched by the element isolation regions even if the isolation width of each element isolation region is made relatively small, specifically, less than 0.3 μm. It is therefore possible to relax or prevent the generation of crystal defects resulting from the stress, thereby reducing occurrence of an undesired leak current between the source and drain of each field effect transistor.

Claims28

Dependent claims

A semiconductor device comprising:

(a) a mask ROM region formed over the main surface of a semiconductor substrate and equipped with a plurality of first field effect transistors;
(b) a plurality of first active regions having the first field effect transistors formed therein, respectively;
and
(c) an element isolation region for electrically isolating the first active regions adjacent to each other,
wherein the element isolation region located in a gate length direction of the first field effect transistors is constructed of a first field plate isolation.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor device and a method of manufacturing the same

Life of this patent

Semiconductor device and a method of manufacturing the same

Life of this patent

Abstract

Claims28