Gate defined schottky diode

A complimentary complementary metal-oxide-semiconductor integrated circuit (CMOS IC) device formed on a substrate having an upper surface, wherein the CMOS IC device comprises:

• a Schottky diode formed on the upper surface, the Schottky diode including:
• a Schottky barrier structure and a backside contact structure formed on the upper surface over first and second doped regions of the substrate, respectively, and
• an isolation structure formed on the upper surface and located between the Schottky barrier and backside contact structures over a third doped region of the substrate;
• and
• a field effect transistor (FET) formed on the upper surface, the FET including:
• first and second terminal structures formed on the upper surface of the substrate over fifth and sixth doped regions of the substrate, respectively, and
• a gate structure formed on the upper surface of the substrate and located between the first and second terminal structures,
• wherein each of the isolation structure of the Schottky diode and the gate structure of the FET includes a polycrystalline silicon structure.

A method for fabricating a complimentary complementary metal-oxide-semiconductor integrated circuit (CMOS IC) device on a substrate having an upper surface, wherein the method comprises:

• forming a well region in the substrate;
• simultaneously forming a Schottky diode on the well region and a field effect transistor (FET) in a second region of the substrate located outside of the well region,
• wherein the Schottky diode includes a Schottky barrier structure and a backside contact structure formed on the upper surface over first and second doped regions of the substrate, respectively, and an isolation structure formed on the upper surface and located between the Schottky barrier and backside contact structures over a third doped region of the substrate,
• wherein the FET includes first and second terminal structures formed on the upper surface of the substrate over fifth and sixth doped regions of the substrate, respectively, and a gate structure formed on the upper surface of the substrate and located between the first and second terminal structures, and
• wherein simultaneously forming the Schottky diode and the FET comprises depositing a layer of polycrystalline silicon over the upper surface of the substrate, and etching the layer of polycrystalline silicon to form a first polycrystalline silicon structure of the isolation structure of the Schottky diode and second polycrystalline silicon structure of the gate structure of the FET.

A method for fabricating a complimentary complementary metal-oxide-semiconductor integrated circuit (CMOS IC) device on a substrate having an upper surface, wherein the method comprises:

• forming a first well region in the substrate having a first conductivity type;
• forming a second well region in the substrate, separated from the first well region, wherein the second well region has a second conductivity type that is opposite to the first conductivity type;
• simultaneously forming a Schottky diode on the first well region and a field effect transistor (FET) in the second well region of the substrate,
• wherein the Schottky diode includes a Schottky barrier structure and a backside contact structure formed on the upper surface over first and second doped regions of the substrate, respectively, and an isolation structure formed on the upper surface and located between the Schottky barrier and backside contact structures over a third doped region of the substrate,
• wherein the FET includes first and second terminal structures formed on the upper surface of the second well region over fifth and sixth doped regions of the substrate, respectively, and a gate structure formed on the upper surface of the substrate and located between the first and second terminal structures, and
• wherein simultaneously forming the Schottky diode and the FET comprises depositing a layer of polycrystalline silicon over the upper surface of the substrate, and etching the layer of polycrystalline silicon to form a first polycrystalline silicon structure of the isolation structure of the Schottky diode and second polycrystalline silicon structure of the gate structure of the FET.